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Tsirkin" , Jason Wang , QEMU Developers , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-arm , Andrey Yurovsky Errors-To: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-devel" X-TUID: wh1YXqi2ATtE On 17/01/2018 18:12, Andrey Smirnov wrote: > On Wed, Jan 17, 2018 at 7:23 AM, Marcel Apfelbaum > wrote: >> >> Hi Peter, >> >> >> On 16/01/2018 16:34, Peter Maydell wrote: >>> >>> On 16 January 2018 at 01:37, Andrey Smirnov >>> wrote: >>>> >>>> Add code needed to get a functional PCI subsytem when using in >>>> conjunction with upstream Linux guest (4.13+). Tested to work agains= t >>>> "e1000e" (network adapter, using MSI interrupts) as well as >>>> "usb-ehci" (USB controller, using legacy PCI interrupts). >>>> >>>> Cc: Peter Maydell >>>> Cc: Jason Wang >>>> Cc: Philippe Mathieu-Daud=C3=A9 >>>> Cc: qemu-devel@nongnu.org >>>> Cc: qemu-arm@nongnu.org >>>> Cc: yurovsky@gmail.com >>>> Signed-off-by: Andrey Smirnov >>>> --- >>>> default-configs/arm-softmmu.mak | 2 + >>>> hw/pci-host/Makefile.objs | 2 + >>>> hw/pci-host/designware.c | 618 >>>> +++++++++++++++++++++++++++++++++++++++ >>>> include/hw/pci-host/designware.h | 93 ++++++ >>>> include/hw/pci/pci_ids.h | 2 + >>>> 5 files changed, 717 insertions(+) >>>> create mode 100644 hw/pci-host/designware.c >>>> create mode 100644 include/hw/pci-host/designware.h >>> >>> I'm not familiar enough with our PCI code to be able to review >>> this, I'm afraid. MST and Marcel are our PCI subsystem maintainers -- >>> could one of you have a look at whether this seems to be a correct >>> implementation of a pcie host controller ? >> >> >> Sadly PCI Host bridges do not have a standard, each HW vendor >> can do pretty much what they want. >> >> That being said, if Andrey can point me to the PCI spec for the Design= ware >> PCI host bridge and what parts they implemented for it I can have a lo= ok, >> sure. >> (I will not be available for a week or so, but right after) >> >=20 > Just in case you still want this: >=20 > To the best of my knowledge, Synposys does not provide specification > for their PCIe IP to general public and I am in no way affiliated with > them, so I don't have any backchannels to get it any other way. >=20 > The next best thing to an actual spec, that I found to be pretty > useful, is PCIe chapter of i.MX6Q Reference Manual > (https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf page > 4049), which is what I used to implement the code in question. >=20 Appreciated. > Last, and probably the most important, "source of truth" was actual > Linux PCIe driver for i.MX/Designware which I used as a sort of > inverse reference implementation. >=20 We did the same for our PVRDMA device implementation :) Thanks, Marcel > Thanks, > Andrey Smirnov >=20