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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id t80sm7364941pgb.88.2018.02.03.13.06.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Feb 2018 13:06:06 -0800 (PST) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <1517324542-6607-1-git-send-email-peter.maydell@linaro.org> <1517324542-6607-3-git-send-email-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Sat, 3 Feb 2018 13:06:04 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 MIME-Version: 1.0 In-Reply-To: <1517324542-6607-3-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 2/7] target/arm: Split "get pending exception info" from "acknowledge it" X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: ag51ZUeK2wqW On 01/30/2018 07:02 AM, Peter Maydell wrote: > Currently armv7m_nvic_acknowledge_irq() does three things: > * make the current highest priority pending interrupt active > * return a bool indicating whether that interrupt is targeting > Secure or NonSecure state > * implicitly tell the caller which is the highest priority > pending interrupt by setting env->v7m.exception > > We need to split these jobs, because v7m_exception_taken() > needs to know whether the pending interrupt targets Secure so > it can choose to stack callee-saves registers or not, but it > must not make the interrupt active until after it has done > that stacking, in case the stacking causes a derived exception. > Similarly, it needs to know the number of the pending interrupt > so it can read the correct vector table entry before the > interrupt is made active, because vector table reads might > also cause a derived exception. > > Create a new armv7m_nvic_get_pending_irq_info() function which simply > returns information about the highest priority pending interrupt, and > use it to rearrange the v7m_exception_taken() code so we don't > acknowledge the exception until we've done all the things which could > possibly cause a derived exception. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 19 ++++++++++++++++--- > hw/intc/armv7m_nvic.c | 30 +++++++++++++++++++++++------- > target/arm/helper.c | 16 ++++++++++++---- > hw/intc/trace-events | 3 ++- > 4 files changed, 53 insertions(+), 15 deletions(-) Reviewed-by: Richard Henderson r~