From: Andrew Jeffery <andrew@codeconstruct.com.au>
To: Coco Li <lixiaoyan@google.com>, peter.maydell@linaro.org, clg@kaod.org
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Felix Wu <flwu@google.com>
Subject: Re: [PATCH 1/5] hw/gpio: Add property for ASPEED GPIO in 32 bits basis
Date: Wed, 10 Sep 2025 13:21:53 +0930 [thread overview]
Message-ID: <e0e733ff458cf253ddaf2b5570183b86c7c13102.camel@codeconstruct.com.au> (raw)
In-Reply-To: <20250903213809.3779860-2-lixiaoyan@google.com>
On Wed, 2025-09-03 at 21:38 +0000, Coco Li wrote:
> From: Felix Wu <flwu@google.com>
>
> Added 32 bits property for ASPEED GPIO. Previously it can only be access in bitwise manner.
>
> This change gives ASPEED similar behavior as Nuvoton.
Can you point me to the Nuvoton functionality? I had a quick look and
couldn't immediately see an equivalent implementation.
Regardless, I'd like to see more motivation in the commit message than
"make it behave like Nuvoton". Can you provide a concrete use-case as
an example?
Andrew
next prev parent reply other threads:[~2025-09-10 3:52 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-03 21:38 [PATCH 0/5] Add Aspeed GPIO test and Support Nuvoton Serial GPIO Expansion (SGPIO) device Coco Li
2025-09-03 21:38 ` [PATCH 1/5] hw/gpio: Add property for ASPEED GPIO in 32 bits basis Coco Li
2025-09-09 7:13 ` Cédric Le Goater
2025-09-10 3:51 ` Andrew Jeffery [this message]
2025-09-12 17:43 ` Coco Li
2025-09-18 0:59 ` Andrew Jeffery
2025-09-03 21:38 ` [PATCH 2/5] tests/qtest: Add qtest for for ASPEED GPIO gpio-set property Coco Li
2025-09-09 7:14 ` Cédric Le Goater
2025-09-03 21:38 ` [PATCH 3/5] hw/arm/npcm8xx.c: Add all IRQ ENUMs Coco Li
2025-09-03 21:38 ` [PATCH 4/5] hw/gpio/npcm8xx: Implement SIOX (SPGIO) device for NPCM without input pin logic Coco Li
2025-09-03 21:38 ` [PATCH 5/5] hw/gpio/npcm8xx: Implement npcm sgpio device " Coco Li
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