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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id u19sm6874950pfl.75.2018.02.23.16.58.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 16:58:56 -0800 (PST) Subject: Re: [PATCH v3 00/31] Add ARMv8.2 half-precision functions To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org References: <20180223153636.29809-1-alex.bennee@linaro.org> From: Richard Henderson Message-ID: Date: Fri, 23 Feb 2018 16:58:55 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-TUID: GDgvQ2nrGWo3 On 02/23/2018 07:36 AM, Alex Bennée wrote: > Now that the softfloat re-factoring has been merged I re-based this > directly from master. Alternatively you can grab the full tree from: > > https://github.com/stsquad/qemu/tree/arm-fp16-v3 > > I've tested with the following RISU test binaries: > > http://people.linaro.org/~alex.bennee/testcases/arm64.risu/testcases.armv8.2_hp.tar.xz > > Which now includes insn_FP1SRC.risu.bin which tests the final patch in > the series which wasn't being exercised by my previous set of tests. > > I've dropped the fp16 patch to both avoid the bikesheding but also > because I could achieve the same effect by running RISU with: > > -cpu cortex-a57 > > The changes are all relatively minor based on feedback. The details > are as usual included in the commit messages bellow ---. Unless I've missed something, that's the whole patch set reviewed. r~