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[209.51.188.17]) by mx.google.com with ESMTPS id a8si290949jam.14.2021.03.04.12.06.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Mar 2021 12:06:20 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ACpEK7LU; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44564 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lHuEm-000730-1y for alex.bennee@linaro.org; Thu, 04 Mar 2021 15:06:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53254) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHuDL-0005p5-59 for qemu-arm@nongnu.org; Thu, 04 Mar 2021 15:04:51 -0500 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:42416) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lHuDJ-0000Hu-Cm for qemu-arm@nongnu.org; Thu, 04 Mar 2021 15:04:50 -0500 Received: by mail-pg1-x52d.google.com with SMTP id o38so19601325pgm.9 for ; Thu, 04 Mar 2021 12:04:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:references:from:message-id:date:user-agent:mime-version :in-reply-to:content-language:content-transfer-encoding; bh=k9p9CBlxkeT7UOqovLbboAwo48ySz/XZI0CgrUXyVxg=; b=ACpEK7LUWw/mZwlhheI1qNjkVnR4B34xFmbw31vil9GV78jVWdQ2jIXR0z6zXBcKu0 C0CTOJf7uHr1WiPXfDctfClCAZT11/n2friG3UlyfRk98rpyF4K/h97kEGC1AIth3v9C GfwkEIHyZx5c36JEFjn4pzyLZdolNW6wJnKaB9+WQwLzL1YxUGoITELVQPbBguNvGk3d lgw4GDJ3M5zCeXrRiVqaskIg/bMZzpTFwf50i5AYa7IdA6IvEraO3f1c6XgdfURlISPE wc1uugx1h8zdIp0iEkqU0WntXx5qHGl6dLYkXOlpM2zo6toGbI1ibs/sjlR+R7x2s/5F AZkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=k9p9CBlxkeT7UOqovLbboAwo48ySz/XZI0CgrUXyVxg=; b=d6rwAvUWqMCeyQbBfWzVE/1wWTUZ69OWKvRm3SF6vXJbc+m0Ib+Uq9dy+1rNF8m8L/ DCDhvjJwVBESi6Ugc4SnNTyU7oHcPmZjH06HxQUXgjS1q2riF7SOXeAztfboVrUBRPBw b/7aH8MNnkcfjLg248OF9qkd/P8Qv30maedZJCTZqJF39RugjL96xrpC/dIxD40rwMuH cpAAsqQRqJ9Uo6xquU0MEtUyB+fth1KKSC5sXXpCV6BfU7el0v7sxQwVbQz8j5SnRCS6 +695vK2TvFMKQVR3ZlHM7Meh8b4DOquozPW0ESYwNMDK5CORHHJyFkk95PZS846e2+Ib EaTg== X-Gm-Message-State: AOAM532AEViESx78XwB29fdTzJNlHJIXBIsVZ4f8BTkI/uWC8oxEvqPJ Is6cUxYasCoFVY/QFvofUNVs0A== X-Received: by 2002:a63:4f59:: with SMTP id p25mr5001131pgl.335.1614888287978; Thu, 04 Mar 2021 12:04:47 -0800 (PST) Received: from [192.168.1.11] ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id i11sm230936pfo.29.2021.03.04.12.04.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Mar 2021 12:04:47 -0800 (PST) Subject: Re: [PATCH 22/44] hw/arm/armsse: Add a define for number of IRQs used by the SSE itself To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210219144617.4782-1-peter.maydell@linaro.org> <20210219144617.4782-23-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Thu, 4 Mar 2021 12:04:45 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 MIME-Version: 1.0 In-Reply-To: <20210219144617.4782-23-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: V24AL5DVwAXU On 2/19/21 6:45 AM, Peter Maydell wrote: > The SSE uses 32 interrupts for its own devices, and then passes through > its expansion IRQ inputs to the CPU's interrupts 33 and upward. > Add a define for the number of IRQs the SSE uses for itself, instead > of hardcoding 32. > > Signed-off-by: Peter Maydell > --- Reviewed-by: Richard Henderson r~