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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i197sm655801pfe.137.2020.03.16.12.36.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Mar 2020 12:36:26 -0700 (PDT) Subject: Re: [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: =?UTF-8?Q?Alex_Benn=c3=a9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , Paolo Bonzini , Peter Maydell References: <20200316160634.3386-1-philmd@redhat.com> <20200316160634.3386-4-philmd@redhat.com> From: Richard Henderson Message-ID: Date: Mon, 16 Mar 2020 12:36:24 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200316160634.3386-4-philmd@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-TUID: HU2B5uynw3ES On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote: > Under KVM the 'Data or unified Cache line Clean by VA to PoP' > instruction will trap. > > Fixes: 0d57b4999 ("Add support for DC CVAP & DC CVADP ins") > Signed-off-by: Philippe Mathieu-Daudé > --- > target/arm/helper.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index b61ee73d18..924deffd65 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6777,7 +6777,7 @@ static const ARMCPRegInfo rndr_reginfo[] = { > REGINFO_SENTINEL > }; > > -#ifndef CONFIG_USER_ONLY > +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) > static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, > uint64_t value) > { > @@ -6820,9 +6820,9 @@ static const ARMCPRegInfo dcpodp_reg[] = { > .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, > REGINFO_SENTINEL > }; > -#endif /*CONFIG_USER_ONLY*/ > +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ I'm not 100% sure how the system regs function under kvm. If they are not used at all, then we should avoid them all en masse an not piecemeal like this. If they are used for something, then we should keep them registered and change the writefn like so: #ifdef CONFIG_TCG /* existing stuff */ #else /* Handled by hardware accelerator. */ g_assert_not_reached(); #endif r~ > > -#endif > +#endif /* TARGET_AARCH64 */ > > static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, > bool isread) > @@ -7929,7 +7929,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) > if (cpu_isar_feature(aa64_rndr, cpu)) { > define_arm_cp_regs(cpu, rndr_reginfo); > } > -#ifndef CONFIG_USER_ONLY > +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) > /* Data Cache clean instructions up to PoP */ > if (cpu_isar_feature(aa64_dcpop, cpu)) { > define_one_arm_cp_reg(cpu, dcpop_reg); > @@ -7938,8 +7938,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) > define_one_arm_cp_reg(cpu, dcpodp_reg); > } > } > -#endif /*CONFIG_USER_ONLY*/ > -#endif > +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ > +#endif /* TARGET_AARCH64 */ > > if (cpu_isar_feature(any_predinv, cpu)) { > define_arm_cp_regs(cpu, predinv_reginfo); >