From: Richard Henderson <richard.henderson@linaro.org>
To: "Alex Bennée" <alex.bennee@linaro.org>, qemu-arm@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v2 15/32] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
Date: Thu, 8 Feb 2018 13:49:39 -0800 [thread overview]
Message-ID: <f9f6893b-3fd7-69ed-c7ae-c54d67897955@linaro.org> (raw)
In-Reply-To: <20180208173157.24705-16-alex.bennee@linaro.org>
On 02/08/2018 09:31 AM, Alex Bennée wrote:
> The helpers use the new re-factored muladd support in SoftFloat for the
> float16 work.
>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> ---
> target/arm/translate-a64.c | 69
> ++++++++++++++++++++++++++++++++++++---------- 1 file changed, 54
> insertions(+), 15 deletions(-)
>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index
> 3a2be1e016..83a1fa3116 100644 --- a/target/arm/translate-a64.c +++
> b/target/arm/translate-a64.c @@ -10804,7 +10804,7 @@ static void
> disas_simd_indexed(DisasContext *s, uint32_t insn) } /* fall through */
> case 0x9: /* FMUL, FMULX */ - if (!extract32(size, 1, 1)) { +
> if (size == 1 || (size < 2 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) {
> unallocated_encoding(s); return; } @@ -10816,18 +10816,30 @@ static void
> disas_simd_indexed(DisasContext *s, uint32_t insn) }
>
> if (is_fp) { - /* low bit of size indicates single/double */ - size =
> extract32(size, 0, 1) ? 3 : 2; - if (size == 2) { + /* convert
> insn encoded size to TCGMemOp size */ + switch (size) { + case 0: /*
> half-precision */ + size = MO_16; + index = h << 2 | l
> << 1 | m; + break;
FWIW, the size check for the integer insns is done in this block (in the !is_fp
side of course). I think it makes sense to do the size check for FP insns down
here too. So, e.g.
if (is_fp) {
switch (size) {
case 2: /* single precision */
...
case 3: /* double precision */
...
case 0: /* half precision */
size = MO_16;
index = ...
is_fp16 = true;
if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
break;
}
/* fallthru */
default: /* unallocated */
unallocated_encoding(s);
return;
}
}
Just below, you have not updated the call to get_fpstatus_ptr.
For the record, for fcmla I needed to introduce an "is_fp16" bool here.
(Since of course a complex fp16 is 32-bits wide.)
r~
next prev parent reply other threads:[~2018-02-08 21:49 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-08 17:31 [PATCH v2 00/32] Add ARMv8.2 half-precision functions Alex Bennée
2018-02-08 17:31 ` [PATCH v2 01/32] include/exec/helper-head.h: support f16 in helper calls Alex Bennée
2018-02-08 17:31 ` [PATCH v2 02/32] target/arm/cpu64: introduce ARM_V8_FP16 feature bit Alex Bennée
2018-02-08 17:31 ` [PATCH v2 03/32] target/arm/cpu64: allow fp16 to be disabled Alex Bennée
2018-02-08 20:36 ` [Qemu-devel] " Richard Henderson
2018-02-13 14:26 ` Peter Maydell
2018-02-21 16:35 ` Alex Bennée
2018-02-21 18:16 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 04/32] target/arm/cpu.h: update comment for half-precision values Alex Bennée
2018-02-08 17:31 ` [PATCH v2 05/32] target/arm/cpu.h: add additional float_status flags Alex Bennée
2018-02-08 20:42 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 06/32] target/arm/helper: pass explicit fpst to set_rmode Alex Bennée
2018-02-08 20:43 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 07/32] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) Alex Bennée
2018-02-08 20:46 ` [Qemu-devel] " Richard Henderson
2018-02-08 20:49 ` Richard Henderson
2018-02-08 17:31 ` [PATCH v2 08/32] arm/translate-a64: handle_3same_64 comment fix Alex Bennée
2018-02-08 20:46 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 09/32] arm/translate-a64: initial decode for simd_three_reg_same_fp16 Alex Bennée
2018-02-08 20:48 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 10/32] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 Alex Bennée
2018-02-08 20:49 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 11/32] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] " Alex Bennée
2018-02-08 20:54 ` [Qemu-devel] " Richard Henderson
2018-02-23 11:59 ` Alex Bennée
2018-02-23 22:10 ` Richard Henderson
2018-02-08 17:31 ` [PATCH v2 12/32] arm/translate-a64: add FP16 FMULA/X/S " Alex Bennée
2018-02-08 20:56 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 13/32] arm/translate-a64: add FP16 FR[ECP/SQRT]S " Alex Bennée
2018-02-08 20:59 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 14/32] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16 Alex Bennée
2018-02-08 21:30 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 15/32] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed Alex Bennée
2018-02-08 21:49 ` Richard Henderson [this message]
2018-02-08 17:31 ` [PATCH v2 16/32] arm/translate-a64: add FP16 x2 ops for simd_indexed Alex Bennée
2018-02-08 22:10 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 17/32] arm/translate-a64: initial decode for simd_two_reg_misc_fp16 Alex Bennée
2018-02-08 22:15 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 18/32] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 Alex Bennée
2018-02-08 22:32 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 19/32] arm/translate-a64: add FCVTxx " Alex Bennée
2018-02-08 22:35 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 20/32] arm/translate-a64: add FP16 FCMxx (zero) " Alex Bennée
2018-02-08 22:39 ` [Qemu-devel] " Richard Henderson
2018-02-22 17:23 ` Alex Bennée
2018-02-22 19:40 ` Richard Henderson
2018-02-23 10:23 ` Alex Bennée
2018-02-08 17:31 ` [PATCH v2 21/32] arm/translate-a64: add FP16 SCVTF/UCVFT " Alex Bennée
2018-02-08 22:42 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 22/32] arm/translate-a64: add FP16 FNEG/FABS " Alex Bennée
2018-02-08 22:43 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 23/32] arm/helper.c: re-factor recpe and add recepe_f16 Alex Bennée
2018-02-09 17:54 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 24/32] arm/translate-a64: add FP16 FRECPE Alex Bennée
2018-02-09 17:57 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 25/32] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 Alex Bennée
2018-02-09 18:00 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 26/32] arm/translate-a64: add FP16 FSQRT " Alex Bennée
2018-02-09 18:01 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 27/32] arm/helper.c: re-factor rsqrte and add rsqrte_f16 Alex Bennée
2018-02-09 18:15 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 28/32] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 Alex Bennée
2018-02-09 18:15 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 29/32] arm/translate-a64: add FP16 FMOV to simd_mod_imm Alex Bennée
2018-02-09 18:23 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 30/32] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise Alex Bennée
2018-02-09 18:27 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 31/32] arm/translate-a64: implement simd_scalar_three_reg_same_fp16 Alex Bennée
2018-02-09 18:34 ` [Qemu-devel] " Richard Henderson
2018-02-08 17:31 ` [PATCH v2 32/32] arm/translate-a64: add all single op FP16 to handle_fp_1src_half Alex Bennée
2018-02-09 18:37 ` [Qemu-devel] " Richard Henderson
2018-02-23 9:45 ` Alex Bennée
2018-02-08 18:49 ` [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions no-reply
2018-02-08 18:56 ` no-reply
2018-02-08 19:04 ` no-reply
2018-02-08 19:11 ` no-reply
2018-02-08 19:17 ` no-reply
2018-02-08 21:33 ` no-reply
2018-02-13 14:27 ` [Qemu-arm] " Peter Maydell
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