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[173.198.77.219]) by smtp.gmail.com with ESMTPSA id r2-v6sm1860795pfa.49.2018.06.12.18.27.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Jun 2018 18:27:41 -0700 (PDT) To: Peter Maydell References: <20180530180120.13355-1-richard.henderson@linaro.org> <20180530180120.13355-16-richard.henderson@linaro.org> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: Date: Tue, 12 Jun 2018 15:27:37 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: Re: [Qemu-arm] [PATCH v3b 15/18] target/arm: Implement SVE Integer Compare - Scalars Group X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , QEMU Developers Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: pBW17n4uDO5n On 06/05/2018 08:02 AM, Peter Maydell wrote: >> + if (count & 63) { >> + d->p[i] = ~(-1ull << (count & 63)) & esz_mask; > > Is this d->p[i] = MAKE_64BIT_MASK(0, count & 63) & esz_mask; ? Fixed. >> + tcg_gen_setcond_i64(cond, cmp, rn, rm); >> + tcg_gen_extrl_i64_i32(cpu_NF, cmp); >> + tcg_temp_free_i64(cmp); >> + >> + /* VF = !NF & !CF. */ >> + tcg_gen_xori_i32(cpu_VF, cpu_NF, 1); >> + tcg_gen_andc_i32(cpu_VF, cpu_VF, cpu_CF); >> + >> + /* Both NF and VF actually look at bit 31. */ >> + tcg_gen_neg_i32(cpu_NF, cpu_NF); >> + tcg_gen_neg_i32(cpu_VF, cpu_VF); > > Microoptimization, but I think you can save an instruction here > using > /* VF = !NF & !CF == !(NF || CF); we know NF and CF are > * both 0 or 1, so the result of the logical NOT has > * VF bit 31 set or clear as required. > */ > tcg_gen_or_i32(cpu_VF, cpu_NF, cpu_CF); > tcg_gen_not_i32(cpu_VF, cpu_VF); No, ~({0,1} | {0,1}) -> {-1,-2}. >> + /* For the helper, compress the different conditions into a computation >> + * of how many iterations for which the condition is true. >> + * >> + * This is slightly complicated by 0 <= UINT64_MAX, which is nominally >> + * 2**64 iterations, overflowing to 0. Of course, predicate registers >> + * aren't that large, so any value >= predicate size is sufficient. >> + */ > > The comment says that 0 <= UINT64_MAX is a special case, > but I don't understand how the code accounts for it ? > >> + tcg_gen_sub_i64(t0, op1, op0); >> + >> + /* t0 = MIN(op1 - op0, vsz). */ >> + if (a->eq) { >> + /* Equality means one more iteration. */ >> + tcg_gen_movi_i64(t1, vsz - 1); >> + tcg_gen_movcond_i64(TCG_COND_LTU, t0, t0, t1, t0, t1); By bounding the input, here, to the vector size. This reduces the (2**64-1)+1 case, which we can't represent, to a vsz+1 case, which we can. This produces the same result for this instruction. This does point out that I should be using the new tcg_gen_umin_i64 helper instead of open-coding with movcond. r~