[PATCH v2 0/2] target/hexagon: event codes

[PATCH v2 0/2] target/hexagon: event codes

[Brian Cain]

Changes in v2:

* Fixed the HEX_EVENT_{INVALID*,PRIV*,etc} - several of these were actually
cause codes, just like TRAP0.
* I combined "Rename HEX_EXCP_ => HEX_EVENT_" and "rename HEX_EVENT_TRAP0=>HEX_CAUSE_TRAP0"
into a single commit.

Brian Cain (2):
  target/hexagon: rename HEX_EXCP_*=>HEX_CAUSE_*
  target/hexagon: add enums for event, cause

 linux-user/hexagon/cpu_loop.c |  4 ++--
 target/hexagon/cpu.h          |  2 +-
 target/hexagon/cpu_bits.h     | 21 ++++++++++++++-------
 target/hexagon/gen_tcg.h      |  2 +-
 target/hexagon/translate.c    |  6 +++---
 5 files changed, 21 insertions(+), 14 deletions(-)

-- 
2.34.1

[PATCH v2 1/2] target/hexagon: rename HEX_EXCP_*=>HEX_CAUSE_*

[Brian Cain]

The values previously used for "HEX_EXCP_*" were the cause code
definitions and not the event numbers.  So in this commit, we update
the names to reflect the cause codes. In HEX_EVENT_TRAP0's case, we add
a new "HEX_EVENT_*" with the correct event number.

Signed-off-by: Brian Cain <bcain@quicinc.com>
---
 linux-user/hexagon/cpu_loop.c |  4 ++--
 target/hexagon/cpu.h          |  2 +-
 target/hexagon/cpu_bits.h     | 15 ++++++++-------
 target/hexagon/gen_tcg.h      |  2 +-
 target/hexagon/translate.c    |  6 +++---
 5 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c
index d41159e52a..40db596301 100644
--- a/linux-user/hexagon/cpu_loop.c
+++ b/linux-user/hexagon/cpu_loop.c
@@ -42,7 +42,7 @@ void cpu_loop(CPUHexagonState *env)
         case EXCP_INTERRUPT:
             /* just indicate that signals should be handled asap */
             break;
-        case HEX_EXCP_TRAP0:
+        case HEX_EVENT_TRAP0:
             syscallnum = env->gpr[6];
             env->gpr[HEX_REG_PC] += 4;
             ret = do_syscall(env,
@@ -60,7 +60,7 @@ void cpu_loop(CPUHexagonState *env)
                 env->gpr[0] = ret;
             }
             break;
-        case HEX_EXCP_PC_NOT_ALIGNED:
+        case HEX_CAUSE_PC_NOT_ALIGNED:
             force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN,
                             env->gpr[HEX_REG_R31]);
             break;
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 764f3c38cc..cb8038d7a8 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -149,7 +149,7 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
     }
     *flags = hex_flags;
     if (*pc & PCALIGN_MASK) {
-        hexagon_raise_exception_err(env, HEX_EXCP_PC_NOT_ALIGNED, 0);
+        hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0);
     }
 }
 
diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index 4279281a71..2e60c0fafe 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon/cpu_bits.h
@@ -23,14 +23,15 @@
 #define PCALIGN 4
 #define PCALIGN_MASK (PCALIGN - 1)
 
-#define HEX_EXCP_FETCH_NO_UPAGE  0x012
-#define HEX_EXCP_INVALID_PACKET  0x015
-#define HEX_EXCP_INVALID_OPCODE  0x015
-#define HEX_EXCP_PC_NOT_ALIGNED  0x01e
-#define HEX_EXCP_PRIV_NO_UREAD   0x024
-#define HEX_EXCP_PRIV_NO_UWRITE  0x025
+#define HEX_EVENT_TRAP0           0x008
 
-#define HEX_EXCP_TRAP0           0x172
+#define HEX_CAUSE_TRAP0           0x172
+#define HEX_CAUSE_FETCH_NO_UPAGE  0x012
+#define HEX_CAUSE_INVALID_PACKET  0x015
+#define HEX_CAUSE_INVALID_OPCODE  0x015
+#define HEX_CAUSE_PC_NOT_ALIGNED  0x01e
+#define HEX_CAUSE_PRIV_NO_UREAD   0x024
+#define HEX_CAUSE_PRIV_NO_UWRITE  0x025
 
 #define PACKET_WORDS_MAX         4
 
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 3fc1f4e281..8a3b801287 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -1365,7 +1365,7 @@
     do { \
         uiV = uiV; \
         tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \
-        TCGv excp = tcg_constant_tl(HEX_EXCP_TRAP0); \
+        TCGv excp = tcg_constant_tl(HEX_EVENT_TRAP0); \
         gen_helper_raise_exception(tcg_env, excp); \
     } while (0)
 #endif
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 4b1bee3c6d..4d03ccbed1 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -591,7 +591,7 @@ static void gen_insn(DisasContext *ctx)
         ctx->insn->generate(ctx);
         mark_store_width(ctx);
     } else {
-        gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE);
+        gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_OPCODE);
     }
 }
 
@@ -968,7 +968,7 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx)
 
     nwords = read_packet_words(env, ctx, words);
     if (!nwords) {
-        gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);
+        gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_PACKET);
         return;
     }
 
@@ -984,7 +984,7 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx)
         gen_commit_packet(ctx);
         ctx->base.pc_next += pkt.encod_pkt_size_in_bytes;
     } else {
-        gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);
+        gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_PACKET);
     }
 }
 
-- 
2.34.1

[PATCH v2 2/2] target/hexagon: add enums for event, cause

[Brian Cain]

Signed-off-by: Brian Cain <bcain@quicinc.com>
---
 target/hexagon/cpu_bits.h | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index 2e60c0fafe..ff596e2a94 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon/cpu_bits.h
@@ -23,15 +23,21 @@
 #define PCALIGN 4
 #define PCALIGN_MASK (PCALIGN - 1)
 
-#define HEX_EVENT_TRAP0           0x008
+enum hex_event {
+    HEX_EVENT_NONE           = -1,
+    HEX_EVENT_TRAP0          =  0x008,
+};
 
-#define HEX_CAUSE_TRAP0           0x172
-#define HEX_CAUSE_FETCH_NO_UPAGE  0x012
-#define HEX_CAUSE_INVALID_PACKET  0x015
-#define HEX_CAUSE_INVALID_OPCODE  0x015
-#define HEX_CAUSE_PC_NOT_ALIGNED  0x01e
-#define HEX_CAUSE_PRIV_NO_UREAD   0x024
-#define HEX_CAUSE_PRIV_NO_UWRITE  0x025
+enum hex_cause {
+    HEX_CAUSE_NONE = -1,
+    HEX_CAUSE_TRAP0 = 0x172,
+    HEX_CAUSE_FETCH_NO_UPAGE =  0x012,
+    HEX_CAUSE_INVALID_PACKET =  0x015,
+    HEX_CAUSE_INVALID_OPCODE =  0x015,
+    HEX_CAUSE_PC_NOT_ALIGNED =  0x01e,
+    HEX_CAUSE_PRIV_NO_UREAD  =  0x024,
+    HEX_CAUSE_PRIV_NO_UWRITE =  0x025,
+};
 
 #define PACKET_WORDS_MAX         4
 
-- 
2.34.1

RE: [PATCH v2 1/2] target/hexagon: rename HEX_EXCP_*=>HEX_CAUSE_*

[ltaylorsimpson]

> -----Original Message-----
> From: Brian Cain <bcain@quicinc.com>
> Sent: Monday, August 26, 2024 6:27 PM
> To: qemu-devel@nongnu.org
> Cc: bcain@quicinc.com; quic_mathbern@quicinc.com;
> sidneym@quicinc.com; quic_mliebel@quicinc.com;
> ltaylorsimpson@gmail.com; Laurent Vivier <laurent@vivier.eu>
> Subject: [PATCH v2 1/2] target/hexagon: rename
> HEX_EXCP_*=>HEX_CAUSE_*
> 
> The values previously used for "HEX_EXCP_*" were the cause code
> definitions and not the event numbers.  So in this commit, we update the
> names to reflect the cause codes. In HEX_EVENT_TRAP0's case, we add a
> new "HEX_EVENT_*" with the correct event number.
> 
> Signed-off-by: Brian Cain <bcain@quicinc.com>
> ---
>  linux-user/hexagon/cpu_loop.c |  4 ++--
>  target/hexagon/cpu.h          |  2 +-
>  target/hexagon/cpu_bits.h     | 15 ++++++++-------
>  target/hexagon/gen_tcg.h      |  2 +-
>  target/hexagon/translate.c    |  6 +++---
>  5 files changed, 15 insertions(+), 14 deletions(-)

Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>

RE: [PATCH v2 2/2] target/hexagon: add enums for event, cause

[ltaylorsimpson]

> -----Original Message-----
> From: Brian Cain <bcain@quicinc.com>
> Sent: Monday, August 26, 2024 6:27 PM
> To: qemu-devel@nongnu.org
> Cc: bcain@quicinc.com; quic_mathbern@quicinc.com;
> sidneym@quicinc.com; quic_mliebel@quicinc.com;
> ltaylorsimpson@gmail.com
> Subject: [PATCH v2 2/2] target/hexagon: add enums for event, cause
> 
> Signed-off-by: Brian Cain <bcain@quicinc.com>
> ---
>  target/hexagon/cpu_bits.h | 22 ++++++++++++++--------
>  1 file changed, 14 insertions(+), 8 deletions(-)

Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>