From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Gmh4z-0003gg-2v for qemu-devel@nongnu.org; Tue, 21 Nov 2006 20:39:13 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Gmh4x-0003eZ-Vw for qemu-devel@nongnu.org; Tue, 21 Nov 2006 20:39:12 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Gmh4x-0003eF-QB for qemu-devel@nongnu.org; Tue, 21 Nov 2006 20:39:11 -0500 Received: from [212.78.202.217] (helo=lmfilto03.st1.spray.net) by monty-python.gnu.org with esmtp (Exim 4.52) id 1Gmh4x-00018t-GB for qemu-devel@nongnu.org; Tue, 21 Nov 2006 20:39:11 -0500 Received: from lmfilto03.st1.spray.net (localhost [127.0.0.1]) by lmfilto03-10027.st1.spray.net (Postfix) with ESMTP id DD32B10CB21 for ; Tue, 21 Nov 2006 21:00:00 +0000 (GMT) Received: from localhost (localhost [127.0.0.1]) by lmfilto03-10025.st1.spray.net (Postfix) with ESMTP id 1E6ED10B7DD for ; Tue, 21 Nov 2006 19:08:35 +0000 (GMT) Received: from ttlaptop (unknown [84.219.16.100]) by lmsmtp01.st1.spray.net (Postfix) with ESMTP id 1A9722688 for ; Tue, 21 Nov 2006 19:08:33 +0000 (GMT) From: =?iso-8859-1?Q?Torbj=F6rn_Andersson?= Date: Tue, 21 Nov 2006 20:08:34 +0100 Message-ID: <000c01c70da0$71d45de0$3101a8c0@ttlaptop> MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_NextPart_000_000D_01C70DA8.D398C5E0" Subject: [Qemu-devel] ARM CPSR and conditional instructions Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. ------=_NextPart_000_000D_01C70DA8.D398C5E0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hello qemu developers! I=B4m using QEMU for some ARM debugging and I have som questions = regardning the CPSR register. I get the feeling that the CPSR condition code bits, representing the results from the ALU, are not maintained at all points. = Is the JIT in QEMU tailored in any way towards GCC output? (Resulting in = issues with the output of other compilers that make use of the conditional execution of instructions etc.) What I want to do is to try to verify QEMU maintains the CPSR register = and if not fix it. However, it is not trivial identify where the updates = should be placed. The relationship between translate.c and op.c is not trival I must say :) I would be happy I anyone here could give me some pointers on how the updates of the CPSR register is done today and what the strategy is. I = guess there are plenty of performance ideas here as in the rest of qemu. Does anyone have any reflection on this topic or can anyone give me some pointers? Torbj=F6rn ------=_NextPart_000_000D_01C70DA8.D398C5E0 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Hello qemu developers!

I=B4m using QEMU for some ARM debugging and I have som questions = regardning the CPSR register. I get the feeling that the CPSR condition code bits, representing the results from the ALU, are not maintained at all points. = Is the JIT in QEMU tailored in any way towards GCC output? (Resulting in issues = with the output of other compilers that make use of the conditional execution = of instructions etc.)

What I want to do is to try to verify QEMU maintains the CPSR register = and if not fix it. However, it is not trivial identify where the updates should = be placed. The relationship between translate.c and op.c is not trival I = must say :)

I would be happy I anyone here could give me = some pointers on how the updates of the CPSR register is done today and what = the strategy is. I guess there are plenty of performance ideas here as in = the rest of qemu.

Does anyone have any reflection on this topic or can anyone give me some pointers?

Torbj=F6rn

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