[Qemu-devel] Patch for OHW bootinfos

["Tero Kaarlela" <tero.kaarlela@kotinet.com>]

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This patches residual data structures for OHW Prep. ftp://ftp.software.ibm.com/rs6000/technology/spec/RESIDUAL.PS has been used as reference document here. Now the Vital product data shows correctly with guest Linux lsresidual utility.(instead of segmentation fault before patching). Also memory segment info structures are correct now but data in segments not(need a dynamical way to add data into these). Also devices structures are corrected but no devices described yet(dynamical detecting of PCI devices is easy but how about ISAPNP?).


Tero 
  

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--- OpenHackWare-release-0.4/src/bootinfos.c	2005-03-31 07:23:33.000000000 +0000
+++ OpenHackWare-release-0.4/src/bootinfos.c.mod	2007-07-20 17:17:55.000000000 +0000
@@ -80,7 +80,7 @@ void prepare_bootinfos (void *p, uint32_
 }
 
 /* Residual data */
-#define MAX_CPUS 16
+#define MAX_CPUS 32
 #define MAX_SEGS 64
 #define MAX_MEMS 64
 #define MAX_DEVS 256
@@ -88,20 +88,21 @@ void prepare_bootinfos (void *p, uint32_
 typedef struct vital_t {
     /* Motherboard dependents */
     uint8_t model[32];
-    uint8_t serial[64];
-    uint16_t version;
-    uint16_t revision;
-    uint32_t firmware;
+    uint8_t serial[16]; 
+    uint8_t reserved[48]; 
+    uint32_t firmwaresupplier;
+    uint32_t firmwaresupports;
     uint32_t NVRAM_size;
     uint32_t nSIMMslots;
-    uint32_t nISAslots;
-    uint32_t nPCIslots;
-    uint32_t nPCMCIAslots;
-    uint32_t nMCAslots;
-    uint32_t nEISAslots;
+    uint16_t endianswitchmethod;
+    uint16_t spreadIOmethod;
+    uint32_t smplar; 
+    uint32_t ramerrorlog;
+    uint8_t reserved5[4];
+    uint8_t reserved6[4]; 	
     uint32_t CPUHz;
     uint32_t busHz;
-    uint32_t PCIHz;
+    uint8_t reserved7[4];
     uint32_t TBdiv;
     /* CPU infos */
     uint32_t wwidth;
@@ -126,14 +127,15 @@ typedef struct vital_t {
     uint32_t ITLB_assoc;
     uint32_t DTLB_size;
     uint32_t DTLB_assoc;
-    void *ext_vital;
+    uint32_t ext_vital;
 } vital_t;
 
 typedef struct PPC_CPU_t {
     uint32_t pvr;
-    uint32_t serial;
-    uint32_t L2_size;
-    uint32_t L2_assoc;
+    uint8_t ncpu;
+    uint8_t statecpu;
+    uint16_t reserved;
+    
 } PPC_CPU_t;
 
 typedef struct map_t {
@@ -151,10 +153,14 @@ typedef struct PPC_device_t {
     uint32_t devID;
     uint32_t serial;
     uint32_t flags;
-    uint32_t type;
-    uint32_t subtype;
-    uint32_t interface;
-    uint32_t spare;
+    uint8_t type;
+    uint8_t subtype;
+    uint8_t interface;
+    uint8_t spare;
+    uint32_t busaccess;
+    uint32_t allocoffset;
+    uint32_t posoffset;
+    uint32_t compatoffset;
 } PPC_device_t;
 
 typedef struct residual_t {
@@ -162,7 +168,8 @@ typedef struct residual_t {
     uint16_t  version;
     uint16_t  revision;
     vital_t   vital;
-    uint32_t  nCPUs;
+    uint16_t  maxnCPUs;
+    uint16_t  nCPUs;
     PPC_CPU_t CPUs[MAX_CPUS];
     uint32_t  max_mem;
     uint32_t  good_mem;
@@ -179,29 +186,34 @@ void residual_build (void *p, uint32_t m
                      uint32_t load_base, uint32_t load_size,
                      uint32_t last_alloc)
 {
-    const unsigned char model[] = "Qemu\0PPC\0";
+    const unsigned char model[] = "OHW PPS Model 6050\0\0\0\0\0\0\0\0\0\0\0\0\0\0";
+    const unsigned char serial[] = "OHW60501\0\0\0\0\0\0\0\0";
+    const unsigned char reserved[] ="\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0";
+    const unsigned char reserved1[] = "\0\0\0\0";
     residual_t *res = p;
     int i;
-
+   
     if (res == NULL)
         return;
     res->length = sizeof(residual_t);
     res->version = 1;
     res->revision = 0;
     memcpy(res->vital.model, model, sizeof(model));
-    res->vital.version = 1;
-    res->vital.revision = 0;
-    res->vital.firmware = 0x1D1;
+    memcpy(res->vital.serial, serial, sizeof(serial));
+    memcpy(res->vital.reserved, reserved, sizeof(reserved));
+    res->vital.firmwaresupplier = 0x00;
+    res->vital.firmwaresupports = 0x1D1;
     res->vital.NVRAM_size = 0x2000;
     res->vital.nSIMMslots = 1;
-    res->vital.nISAslots = 0;
-    res->vital.nPCIslots = 0;
-    res->vital.nPCMCIAslots = 0;
-    res->vital.nMCAslots = 0;
-    res->vital.nEISAslots = 0;
+    res->vital.endianswitchmethod = 0x01;
+    res->vital.spreadIOmethod = 0x00;
+    res->vital.smplar = 0;
+    res->vital.ramerrorlog = 0;
+    memcpy(res->vital.reserved5, reserved1, sizeof(reserved1));
+    memcpy(res->vital.reserved6, reserved1, sizeof(reserved1));
     res->vital.CPUHz = 200 * 1000 * 1000;
     res->vital.busHz = 100 * 1000 * 1000;
-    res->vital.PCIHz = 33 * 1000 * 1000;
+    memcpy(res->vital.reserved7, reserved1, sizeof(reserved1));
     res->vital.TBdiv = 1000;
     res->vital.wwidth = 32;
     res->vital.page_size = 4096;
@@ -224,39 +236,46 @@ void residual_build (void *p, uint32_t m
     res->vital.ITLB_assoc = 2;
     res->vital.DTLB_size = 0;
     res->vital.DTLB_assoc = 2;
-    res->vital.ext_vital = NULL;
+    res->vital.ext_vital = 0;
+    res->maxnCPUs = 1;
     res->nCPUs = 1;
     res->CPUs[0].pvr = mfpvr();
-    res->CPUs[0].serial = 0;
-    res->CPUs[0].L2_size = 0;
-    res->CPUs[0].L2_assoc = 8;
+    res->CPUs[0].ncpu = 0;
+    res->CPUs[0].statecpu = 0;
+    res->CPUs[0].reserved = 0;
+    for(i = 1; i < 31; i++) {
+    res->CPUs[i].pvr = 0;
+    res->CPUs[i].ncpu = i;
+    res->CPUs[i].statecpu = 0xFF;
+	}
     /* Memory infos */
     res->max_mem = memsize;
     res->good_mem = memsize;
+    res->nmaps = 6;
     /* Memory mappings */
     /* First segment: firmware */
     last_alloc = (last_alloc + 4095) & ~4095;
-    res->maps[0].usage = 0x0007;
-    res->maps[0].base  = 0x00000000;
-    res->maps[0].count = last_alloc >> 12;
+    res->maps[0].usage = 0x0004;
+    res->maps[0].base  = 0x0580;			    
+    res->maps[0].count = 0x0021;
     i = 1;
     if (last_alloc != load_base) {
         /* Free memory between firmware and boot image */
         res->maps[1].usage = 0x0010;
-        res->maps[1].base = last_alloc >> 12;
-        res->maps[1].count = (load_base - last_alloc) >> 12;
+        res->maps[1].base = 0x0600;
+        res->maps[1].count = 0;
         i++;
     }
     /* Boot image */
     load_size = (load_size + 4095) & ~4095;
     res->maps[i].usage = 0x0008;
-    res->maps[i].base  = load_base >> 12;
-    res->maps[i].count = load_size >> 12;
+    res->maps[i].base  = 0x0100;
+    res->maps[i].count = 0x0100;
     i++;
     /* Free memory */
     res->maps[i].usage = 0x0010;
-    res->maps[i].base  = (load_base + load_size) >> 12;
-    res->maps[i].count = (memsize >> 12) - res->maps[i].base;
+    res->maps[i].base  = 0x0040;
+    res->maps[i].count = 0x400;
     i++;
     /* ISA IO region : 8MB */
     res->maps[i].usage = 0x0040;
@@ -273,10 +292,27 @@ void residual_build (void *p, uint32_t m
     res->maps[i].base  = 0xFFFF0000 >> 12;
     res->maps[i].count = 0x00010000 >> 12;
     i++;
-    res->nmaps = i;
+    for( i = i; i < 64; i++){
+    res->maps[i].usage = 0;
+    res->maps[i].base  = 0;
+    res->maps[i].count = 0;
+    }
     /* Memory SIMMs */
     res->nmems = 1;
     res->memories[0].size = memsize;
     /* Describe no devices */
-    res->ndevices = 0;
+    for(i = 0; i < 255; i++){
+    res->devices[i].busID = 0;
+    res->devices[i].devID = 0;
+    res->devices[i].serial = 0;
+    res->devices[i].flags = 0;
+    res->devices[i].subtype = 0;
+    res->devices[i].interface = 0;
+    res->devices[i].spare = 0;
+    res->devices[i].busaccess = 0;
+    res->devices[i].allocoffset = 0;
+    res->devices[i].posoffset = 0;
+    res->devices[i].compatoffset = 0;
+
+}
 }