From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IBtei-0003yM-OE for qemu-devel@nongnu.org; Fri, 20 Jul 2007 10:40:32 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IBteg-0003v3-1v for qemu-devel@nongnu.org; Fri, 20 Jul 2007 10:40:32 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IBtef-0003uz-Q6 for qemu-devel@nongnu.org; Fri, 20 Jul 2007 10:40:29 -0400 Received: from smtpout.kotinet.com ([212.50.215.76]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1IBtef-0004ZT-0Z for qemu-devel@nongnu.org; Fri, 20 Jul 2007 10:40:29 -0400 Received: from kone (adsl-82-141-76-54.kotinet.com [82.141.76.54]) by smtpout.kotinet.com (Postfix) with SMTP id CD8999295F for ; Fri, 20 Jul 2007 17:40:01 +0300 (EEST) Message-ID: <001201c7cade$8118b8e0$ba00a8c0@kone> From: "Tero Kaarlela" Date: Fri, 20 Jul 2007 17:58:59 +0300 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_000E_01C7CAF7.A63D5A40" Subject: [Qemu-devel] Patch for OHW bootinfos Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. ------=_NextPart_000_000E_01C7CAF7.A63D5A40 Content-Type: multipart/alternative; boundary="----=_NextPart_001_000F_01C7CAF7.A63FCB40" ------=_NextPart_001_000F_01C7CAF7.A63FCB40 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable This patches residual data structures for OHW Prep. = ftp://ftp.software.ibm.com/rs6000/technology/spec/RESIDUAL.PS has been = used as reference document here. Now the Vital product data shows = correctly with guest Linux lsresidual utility.(instead of segmentation = fault before patching). Also memory segment info structures are correct = now but data in segments not(need a dynamical way to add data into = these). Also devices structures are corrected but no devices described = yet(dynamical detecting of PCI devices is easy but how about ISAPNP?). Tero=20 ------=_NextPart_001_000F_01C7CAF7.A63FCB40 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

This patches residual data structures = for OHW Prep.=20 ft= p://ftp.software.ibm.com/rs6000/technology/spec/RESIDUAL.PS has = been used as reference document here. Now the Vital product = data shows=20 correctly with guest Linux lsresidual utility.(instead of segmentation = fault=20 before patching). Also memory segment info structures are correct now = but data=20 in segments not(need a dynamical way to add data into these). Also = devices=20 structures are corrected but no devices described yet(dynamical = detecting of PCI=20 devices is easy but how about ISAPNP?).

Tero

------=_NextPart_001_000F_01C7CAF7.A63FCB40-- ------=_NextPart_000_000E_01C7CAF7.A63D5A40 Content-Type: application/octet-stream; name="bootinfos.diff" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="bootinfos.diff" --- OpenHackWare-release-0.4/src/bootinfos.c 2005-03-31 = 07:23:33.000000000 +0000 +++ OpenHackWare-release-0.4/src/bootinfos.c.mod 2007-07-20 = 17:17:55.000000000 +0000 @@ -80,7 +80,7 @@ void prepare_bootinfos (void *p, uint32_ } =20 /* Residual data */ -#define MAX_CPUS 16 +#define MAX_CPUS 32 #define MAX_SEGS 64 #define MAX_MEMS 64 #define MAX_DEVS 256 @@ -88,20 +88,21 @@ void prepare_bootinfos (void *p, uint32_ typedef struct vital_t { /* Motherboard dependents */ uint8_t model[32]; - uint8_t serial[64]; - uint16_t version; - uint16_t revision; - uint32_t firmware; + uint8_t serial[16];=20 + uint8_t reserved[48];=20 + uint32_t firmwaresupplier; + uint32_t firmwaresupports; uint32_t NVRAM_size; uint32_t nSIMMslots; - uint32_t nISAslots; - uint32_t nPCIslots; - uint32_t nPCMCIAslots; - uint32_t nMCAslots; - uint32_t nEISAslots; + uint16_t endianswitchmethod; + uint16_t spreadIOmethod; + uint32_t smplar;=20 + uint32_t ramerrorlog; + uint8_t reserved5[4]; + uint8_t reserved6[4]; =09 uint32_t CPUHz; uint32_t busHz; - uint32_t PCIHz; + uint8_t reserved7[4]; uint32_t TBdiv; /* CPU infos */ uint32_t wwidth; @@ -126,14 +127,15 @@ typedef struct vital_t { uint32_t ITLB_assoc; uint32_t DTLB_size; uint32_t DTLB_assoc; - void *ext_vital; + uint32_t ext_vital; } vital_t; =20 typedef struct PPC_CPU_t { uint32_t pvr; - uint32_t serial; - uint32_t L2_size; - uint32_t L2_assoc; + uint8_t ncpu; + uint8_t statecpu; + uint16_t reserved; + =20 } PPC_CPU_t; =20 typedef struct map_t { @@ -151,10 +153,14 @@ typedef struct PPC_device_t { uint32_t devID; uint32_t serial; uint32_t flags; - uint32_t type; - uint32_t subtype; - uint32_t interface; - uint32_t spare; + uint8_t type; + uint8_t subtype; + uint8_t interface; + uint8_t spare; + uint32_t busaccess; + uint32_t allocoffset; + uint32_t posoffset; + uint32_t compatoffset; } PPC_device_t; =20 typedef struct residual_t { @@ -162,7 +168,8 @@ typedef struct residual_t { uint16_t version; uint16_t revision; vital_t vital; - uint32_t nCPUs; + uint16_t maxnCPUs; + uint16_t nCPUs; PPC_CPU_t CPUs[MAX_CPUS]; uint32_t max_mem; uint32_t good_mem; @@ -179,29 +186,34 @@ void residual_build (void *p, uint32_t m uint32_t load_base, uint32_t load_size, uint32_t last_alloc) { - const unsigned char model[] =3D "Qemu\0PPC\0"; + const unsigned char model[] =3D "OHW PPS Model = 6050\0\0\0\0\0\0\0\0\0\0\0\0\0\0"; + const unsigned char serial[] =3D "OHW60501\0\0\0\0\0\0\0\0"; + const unsigned char reserved[] = =3D"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\= 0\0\0\0\0\0\0\0\0\0\0\0\0\0"; + const unsigned char reserved1[] =3D "\0\0\0\0"; residual_t *res =3D p; int i; - + =20 if (res =3D=3D NULL) return; res->length =3D sizeof(residual_t); res->version =3D 1; res->revision =3D 0; memcpy(res->vital.model, model, sizeof(model)); - res->vital.version =3D 1; - res->vital.revision =3D 0; - res->vital.firmware =3D 0x1D1; + memcpy(res->vital.serial, serial, sizeof(serial)); + memcpy(res->vital.reserved, reserved, sizeof(reserved)); + res->vital.firmwaresupplier =3D 0x00; + res->vital.firmwaresupports =3D 0x1D1; res->vital.NVRAM_size =3D 0x2000; res->vital.nSIMMslots =3D 1; - res->vital.nISAslots =3D 0; - res->vital.nPCIslots =3D 0; - res->vital.nPCMCIAslots =3D 0; - res->vital.nMCAslots =3D 0; - res->vital.nEISAslots =3D 0; + res->vital.endianswitchmethod =3D 0x01; + res->vital.spreadIOmethod =3D 0x00; + res->vital.smplar =3D 0; + res->vital.ramerrorlog =3D 0; + memcpy(res->vital.reserved5, reserved1, sizeof(reserved1)); + memcpy(res->vital.reserved6, reserved1, sizeof(reserved1)); res->vital.CPUHz =3D 200 * 1000 * 1000; res->vital.busHz =3D 100 * 1000 * 1000; - res->vital.PCIHz =3D 33 * 1000 * 1000; + memcpy(res->vital.reserved7, reserved1, sizeof(reserved1)); res->vital.TBdiv =3D 1000; res->vital.wwidth =3D 32; res->vital.page_size =3D 4096; @@ -224,39 +236,46 @@ void residual_build (void *p, uint32_t m res->vital.ITLB_assoc =3D 2; res->vital.DTLB_size =3D 0; res->vital.DTLB_assoc =3D 2; - res->vital.ext_vital =3D NULL; + res->vital.ext_vital =3D 0; + res->maxnCPUs =3D 1; res->nCPUs =3D 1; res->CPUs[0].pvr =3D mfpvr(); - res->CPUs[0].serial =3D 0; - res->CPUs[0].L2_size =3D 0; - res->CPUs[0].L2_assoc =3D 8; + res->CPUs[0].ncpu =3D 0; + res->CPUs[0].statecpu =3D 0; + res->CPUs[0].reserved =3D 0; + for(i =3D 1; i < 31; i++) { + res->CPUs[i].pvr =3D 0; + res->CPUs[i].ncpu =3D i; + res->CPUs[i].statecpu =3D 0xFF; + } /* Memory infos */ res->max_mem =3D memsize; res->good_mem =3D memsize; + res->nmaps =3D 6; /* Memory mappings */ /* First segment: firmware */ last_alloc =3D (last_alloc + 4095) & ~4095; - res->maps[0].usage =3D 0x0007; - res->maps[0].base =3D 0x00000000; - res->maps[0].count =3D last_alloc >> 12; + res->maps[0].usage =3D 0x0004; + res->maps[0].base =3D 0x0580; =20 + res->maps[0].count =3D 0x0021; i =3D 1; if (last_alloc !=3D load_base) { /* Free memory between firmware and boot image */ res->maps[1].usage =3D 0x0010; - res->maps[1].base =3D last_alloc >> 12; - res->maps[1].count =3D (load_base - last_alloc) >> 12; + res->maps[1].base =3D 0x0600; + res->maps[1].count =3D 0; i++; } /* Boot image */ load_size =3D (load_size + 4095) & ~4095; res->maps[i].usage =3D 0x0008; - res->maps[i].base =3D load_base >> 12; - res->maps[i].count =3D load_size >> 12; + res->maps[i].base =3D 0x0100; + res->maps[i].count =3D 0x0100; i++; /* Free memory */ res->maps[i].usage =3D 0x0010; - res->maps[i].base =3D (load_base + load_size) >> 12; - res->maps[i].count =3D (memsize >> 12) - res->maps[i].base; + res->maps[i].base =3D 0x0040; + res->maps[i].count =3D 0x400; i++; /* ISA IO region : 8MB */ res->maps[i].usage =3D 0x0040; @@ -273,10 +292,27 @@ void residual_build (void *p, uint32_t m res->maps[i].base =3D 0xFFFF0000 >> 12; res->maps[i].count =3D 0x00010000 >> 12; i++; - res->nmaps =3D i; + for( i =3D i; i < 64; i++){ + res->maps[i].usage =3D 0; + res->maps[i].base =3D 0; + res->maps[i].count =3D 0; + } /* Memory SIMMs */ res->nmems =3D 1; res->memories[0].size =3D memsize; /* Describe no devices */ - res->ndevices =3D 0; + for(i =3D 0; i < 255; i++){ + res->devices[i].busID =3D 0; + res->devices[i].devID =3D 0; + res->devices[i].serial =3D 0; + res->devices[i].flags =3D 0; + res->devices[i].subtype =3D 0; + res->devices[i].interface =3D 0; + res->devices[i].spare =3D 0; + res->devices[i].busaccess =3D 0; + res->devices[i].allocoffset =3D 0; + res->devices[i].posoffset =3D 0; + res->devices[i].compatoffset =3D 0; + +} } ------=_NextPart_000_000E_01C7CAF7.A63D5A40--