[Qemu-devel] [PATCH] target-mips: add CPU definition for MIPS-II

[Qemu-devel] [PATCH] target-mips: add CPU definition for MIPS-II

[Vasileios Kalintiris]

Add mips2-generic among CPU definitions for MIPS.

Signed-off-by: Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com>
---
 target-mips/translate_init.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 148b394..d4b1cd8 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -108,6 +108,29 @@ struct mips_def_t {
 static const mips_def_t mips_defs[] =
 {
     {
+        /* A generic CPU providing MIPS-II features.
+           FIXME: Eventually this should be replaced by a real CPU model. */
+        .name = "mips2-generic",
+        .CP0_PRid = 0x00018000,
+        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
+        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+                      (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                      (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+                      (0 << CP0C1_CA),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = MIPS_CONFIG3,
+        .CP0_LLAddr_rw_bitmask = 0,
+        .CP0_LLAddr_shift = 4,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x30000011,
+        .CP1_fcr0 = (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S),
+        .SEGBITS = 32,
+        .PABITS = 32,
+        .insn_flags = CPU_MIPS2,
+        .mmu_type = MMU_TYPE_R4000,
+    },
+    {
         .name = "4Kc",
         .CP0_PRid = 0x00018000,
         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
-- 

Re: [Qemu-devel] [PATCH] target-mips: add CPU definition for MIPS-II

[Vasileios Kalintiris]

________________________________________
From: Vasileios Kalintiris
Sent: 25 November 2014 11:04
To: qemu-devel@nongnu.org
Cc: Leon Alrae; aurelien@aurel32.net
Subject: [PATCH] target-mips: add CPU definition for MIPS-II

Add mips2-generic among CPU definitions for MIPS.

Signed-off-by: Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com>
---
 target-mips/translate_init.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 148b394..d4b1cd8 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -108,6 +108,29 @@ struct mips_def_t {
 static const mips_def_t mips_defs[] =
 {
     {
+        /* A generic CPU providing MIPS-II features.
+           FIXME: Eventually this should be replaced by a real CPU model. */
+        .name = "mips2-generic",
+        .CP0_PRid = 0x00018000,
+        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
+        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+                      (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                      (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+                      (0 << CP0C1_CA),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = MIPS_CONFIG3,
+        .CP0_LLAddr_rw_bitmask = 0,
+        .CP0_LLAddr_shift = 4,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x30000011,
+        .CP1_fcr0 = (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S),
+        .SEGBITS = 32,
+        .PABITS = 32,
+        .insn_flags = CPU_MIPS2,
+        .mmu_type = MMU_TYPE_R4000,
+    },
+    {
         .name = "4Kc",
         .CP0_PRid = 0x00018000,
         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
--

ping

Re: [Qemu-devel] [PATCH] target-mips: add CPU definition for MIPS-II

[Petar Jovanovic]

[-- Attachment #1: Type: text/plain, Size: 1997 bytes --]

Adding (another) generic model for an old ISA revision is rather

discouraged in QEMU trunk. Can you add a particular real CPU model?

 

Regards,

Petar

________________________________________

From: Vasileios Kalintiris

Sent: 25 November 2014 11:04

To: address@hidden

Cc: Leon Alrae; address@hidden

Subject: [PATCH] target-mips: add CPU definition for MIPS-II

 

Add mips2-generic among CPU definitions for MIPS.

 

Signed-off-by: Vasileios Kalintiris <address@hidden>

---

target-mips/translate_init.c | 23 +++++++++++++++++++++++

1 file changed, 23 insertions(+)

 

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c

index 148b394..d4b1cd8 100644

--- a/target-mips/translate_init.c

+++ b/target-mips/translate_init.c

@@ -108,6 +108,29 @@ struct mips_def_t {

static const mips_def_t mips_defs[] =

{

     {

+        /* A generic CPU providing MIPS-II features.

+           FIXME: Eventually this should be replaced by a real CPU model.
*/

+        .name = "mips2-generic",

+        .CP0_PRid = 0x00018000,

+        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),

+        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |

+                      (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |

+                      (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |

+                      (0 << CP0C1_CA),

+        .CP0_Config2 = MIPS_CONFIG2,

+        .CP0_Config3 = MIPS_CONFIG3,

+        .CP0_LLAddr_rw_bitmask = 0,

+        .CP0_LLAddr_shift = 4,

+        .SYNCI_Step = 32,

+        .CCRes = 2,

+        .CP0_Status_rw_bitmask = 0x30000011,

+        .CP1_fcr0 = (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S),

+        .SEGBITS = 32,

+        .PABITS = 32,

+        .insn_flags = CPU_MIPS2,

+        .mmu_type = MMU_TYPE_R4000,

+    },

+    {

         .name = "4Kc",

         .CP0_PRid = 0x00018000,

         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),

--

 

ping

 


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Re: [Qemu-devel] [PATCH] target-mips: add CPU definition for MIPS-II

[Vasileios Kalintiris]

[-- Attachment #1: Type: text/plain, Size: 3250 bytes --]

Hello Petar,

I've seen some older threads in the mailing list and I'm aware that
adding generic CPU definitions is something that should be avoided.
However, I don't have any real MIPS-II machine readily available at
the moment.

We need support for the MIPS-II ISA because we enabled the MIPS-II
target in the Clang/LLVM projects and we are running the LLVM
test-suite under QEMU. This allows us to verify that we are not
emitting invalid instructions or instructions that belong to another
version of the ISA. Also, Debian targets MIPS-II for compatibility
reasons and testing the code generation of the compiler for that ISA
is rather important.

So there's an actual need for a MIPS-II definition and it wouldn't
be convenient to have to maintain out-of-tree support for MIPS-II

If this is really problematic for qemu, why don't we add an
--enable-experimental-targets, --enable-generic-targets or something
similar for generic/old CPU definitions?

Thanks,
Vasileios Kalintiris

________________________________
From: Petar Jovanovic [petar.jovanovic@rt-rk.com]
Sent: 01 December 2014 23:45
To: Vasileios Kalintiris
Cc: qemu-devel@nongnu.org; Leon Alrae
Subject: RE: [PATCH] target-mips: add CPU definition for MIPS-II

Adding (another) generic model for an old ISA revision is rather
discouraged in QEMU trunk. Can you add a particular real CPU model?

Regards,
Petar
________________________________________
From: Vasileios Kalintiris
Sent: 25 November 2014 11:04
To: address@hidden
Cc: Leon Alrae; address@hidden
Subject: [PATCH] target-mips: add CPU definition for MIPS-II

Add mips2-generic among CPU definitions for MIPS.

Signed-off-by: Vasileios Kalintiris <address@hidden>
---
target-mips/translate_init.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 148b394..d4b1cd8 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -108,6 +108,29 @@ struct mips_def_t {
static const mips_def_t mips_defs[] =
{
     {
+        /* A generic CPU providing MIPS-II features.
+           FIXME: Eventually this should be replaced by a real CPU model. */
+        .name = "mips2-generic",
+        .CP0_PRid = 0x00018000,
+        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
+        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+                      (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                      (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+                      (0 << CP0C1_CA),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = MIPS_CONFIG3,
+        .CP0_LLAddr_rw_bitmask = 0,
+        .CP0_LLAddr_shift = 4,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x30000011,
+        .CP1_fcr0 = (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S),
+        .SEGBITS = 32,
+        .PABITS = 32,
+        .insn_flags = CPU_MIPS2,
+        .mmu_type = MMU_TYPE_R4000,
+    },
+    {
         .name = "4Kc",
         .CP0_PRid = 0x00018000,
         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
--

ping


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Re: [Qemu-devel] [PATCH] target-mips: add CPU definition for MIPS-II

[Daniel Sanders]

[-- Attachment #1: Type: text/plain, Size: 4160 bytes --]

Hi,

FWIW, the R6000 was a MIPS-II processor but I understand there was never a proper manual for it. http://www.linux-mips.org/wiki/R6000 has a small amount of information but not enough to accurately fill in qemu's structure.

> If this is really problematic for qemu, why don't we add an
> --enable-experimental-targets, --enable-generic-targets or something
> similar for generic/old CPU definitions?

One other possibility is to use a real CPU name such as R6000 but use reasonable guesses where information is unavailable. Is that a good compromise?

Daniel Sanders
Leading Software Design Engineer, MIPS Processor IP
Imagination Technologies Limited
www.imgtec.com<http://www.imgtec.com/>

From: Vasileios Kalintiris
Sent: 15 December 2014 10:09
To: Petar Jovanovic
Cc: qemu-devel@nongnu.org; Leon Alrae; Daniel Sanders
Subject: RE: [PATCH] target-mips: add CPU definition for MIPS-II

Hello Petar,

I've seen some older threads in the mailing list and I'm aware that
adding generic CPU definitions is something that should be avoided.
However, I don't have any real MIPS-II machine readily available at
the moment.

We need support for the MIPS-II ISA because we enabled the MIPS-II
target in the Clang/LLVM projects and we are running the LLVM
test-suite under QEMU. This allows us to verify that we are not
emitting invalid instructions or instructions that belong to another
version of the ISA. Also, Debian targets MIPS-II for compatibility
reasons and testing the code generation of the compiler for that ISA
is rather important.

So there's an actual need for a MIPS-II definition and it wouldn't
be convenient to have to maintain out-of-tree support for MIPS-II

If this is really problematic for qemu, why don't we add an
--enable-experimental-targets, --enable-generic-targets or something
similar for generic/old CPU definitions?

Thanks,
Vasileios Kalintiris
________________________________
From: Petar Jovanovic [petar.jovanovic@rt-rk.com]
Sent: 01 December 2014 23:45
To: Vasileios Kalintiris
Cc: qemu-devel@nongnu.org; Leon Alrae
Subject: RE: [PATCH] target-mips: add CPU definition for MIPS-II
Adding (another) generic model for an old ISA revision is rather
discouraged in QEMU trunk. Can you add a particular real CPU model?

Regards,
Petar
________________________________________
From: Vasileios Kalintiris
Sent: 25 November 2014 11:04
To: address@hidden
Cc: Leon Alrae; address@hidden
Subject: [PATCH] target-mips: add CPU definition for MIPS-II

Add mips2-generic among CPU definitions for MIPS.

Signed-off-by: Vasileios Kalintiris <address@hidden>
---
target-mips/translate_init.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 148b394..d4b1cd8 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -108,6 +108,29 @@ struct mips_def_t {
static const mips_def_t mips_defs[] =
{
     {
+        /* A generic CPU providing MIPS-II features.
+           FIXME: Eventually this should be replaced by a real CPU model. */
+        .name = "mips2-generic",
+        .CP0_PRid = 0x00018000,
+        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
+        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+                      (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                      (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+                      (0 << CP0C1_CA),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = MIPS_CONFIG3,
+        .CP0_LLAddr_rw_bitmask = 0,
+        .CP0_LLAddr_shift = 4,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x30000011,
+        .CP1_fcr0 = (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S),
+        .SEGBITS = 32,
+        .PABITS = 32,
+        .insn_flags = CPU_MIPS2,
+        .mmu_type = MMU_TYPE_R4000,
+    },
+    {
         .name = "4Kc",
         .CP0_PRid = 0x00018000,
         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
--

ping


[-- Attachment #2: Type: text/html, Size: 22241 bytes --]

Re: [Qemu-devel] [PATCH] target-mips: add CPU definition for MIPS-II

[Petar Jovanovic]

Attempt to add a real model is for sure better option than adding a
plain generic model.

As there will be a need to verify the support for MIPS2, we should aim
for the platform that we can physically get at some point and use for
testing/verification and improvement of the model. Untested support is
not what you would benefit from, even if it is only for the sake of
checking whether the instructions belong to MIPS2 set or not. Speaking
of which, if that is the main purpose you would like to use QEMU for,
bear in mind that successful execution of a program does not mean the
program is free of illegal instructions.

Regards,
Petar

From: Daniel Sanders [mailto:Daniel.Sanders@imgtec.com] 
Sent: Monday, December 15, 2014 3:03 PM
To: Vasileios Kalintiris; Petar Jovanovic
Cc: qemu-devel@nongnu.org; Leon Alrae
Subject: RE: [PATCH] target-mips: add CPU definition for MIPS-II

Hi,

FWIW, the R6000 was a MIPS-II processor but I understand there was never a
proper manual for it. http://www.linux-mips.org/wiki/R6000 has a small
amount of information but not enough to accurately fill in qemu's structure.

> If this is really problematic for qemu, why don't we add an
> --enable-experimental-targets, --enable-generic-targets or something
> similar for generic/old CPU definitions?

One other possibility is to use a real CPU name such as R6000 but use
reasonable guesses where information is unavailable. Is that a good
compromise?

Daniel Sanders
Leading Software Design Engineer, MIPS Processor IP
Imagination Technologies Limited
www.imgtec.com

From: Vasileios Kalintiris 
Sent: 15 December 2014 10:09
To: Petar Jovanovic
Cc: qemu-devel@nongnu.org; Leon Alrae; Daniel Sanders
Subject: RE: [PATCH] target-mips: add CPU definition for MIPS-II

Hello Petar,

I've seen some older threads in the mailing list and I'm aware that
adding generic CPU definitions is something that should be avoided.
However, I don't have any real MIPS-II machine readily available at
the moment.

We need support for the MIPS-II ISA because we enabled the MIPS-II
target in the Clang/LLVM projects and we are running the LLVM
test-suite under QEMU. This allows us to verify that we are not
emitting invalid instructions or instructions that belong to another
version of the ISA. Also, Debian targets MIPS-II for compatibility
reasons and testing the code generation of the compiler for that ISA
is rather important.

So there's an actual need for a MIPS-II definition and it wouldn't
be convenient to have to maintain out-of-tree support for MIPS-II

If this is really problematic for qemu, why don't we add an
--enable-experimental-targets, --enable-generic-targets or something
similar for generic/old CPU definitions?

Thanks,
Vasileios Kalintiris
________________________________________
From: Petar Jovanovic [petar.jovanovic@rt-rk.com]
Sent: 01 December 2014 23:45
To: Vasileios Kalintiris
Cc: qemu-devel@nongnu.org; Leon Alrae
Subject: RE: [PATCH] target-mips: add CPU definition for MIPS-II
Adding (another) generic model for an old ISA revision is rather
discouraged in QEMU trunk. Can you add a particular real CPU model?
 
Regards,
Petar
________________________________________
From: Vasileios Kalintiris
Sent: 25 November 2014 11:04
To: address@hidden
Cc: Leon Alrae; address@hidden
Subject: [PATCH] target-mips: add CPU definition for MIPS-II
 
Add mips2-generic among CPU definitions for MIPS.
 
Signed-off-by: Vasileios Kalintiris <address@hidden>
---
target-mips/translate_init.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
 
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 148b394..d4b1cd8 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -108,6 +108,29 @@ struct mips_def_t {
static const mips_def_t mips_defs[] =
{
     {
+        /* A generic CPU providing MIPS-II features.
+           FIXME: Eventually this should be replaced by a real CPU model.
*/
+        .name = "mips2-generic",
+        .CP0_PRid = 0x00018000,
+        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
+        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+                      (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                      (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+                      (0 << CP0C1_CA),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = MIPS_CONFIG3,
+        .CP0_LLAddr_rw_bitmask = 0,
+        .CP0_LLAddr_shift = 4,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x30000011,
+        .CP1_fcr0 = (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S),
+        .SEGBITS = 32,
+        .PABITS = 32,
+        .insn_flags = CPU_MIPS2,
+        .mmu_type = MMU_TYPE_R4000,
+    },
+    {
         .name = "4Kc",
         .CP0_PRid = 0x00018000,
         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
--
 
ping
 

Re: [Qemu-devel] [PATCH] target-mips: add CPU definition for MIPS-II

[Daniel Sanders]

> As there will be a need to verify the support for MIPS2, we should aim
> for the platform that we can physically get at some point and use for
> testing/verification and improvement of the model.

I agree. I'm not sure where I'm likely to find one though.

> Untested support is not what you would benefit from, even if it is only
> for the sake of checking whether the instructions belong to MIPS2 set or not.

I don't completely agree with you here. Tested and verified support is obviously best but even if qemu's support isn't perfectly verified, having a second independent opinion on the correct behaviour is still valuable. In theory, we're unlikely to share the same bugs.

> Speaking of which, if that is the main purpose you would like to use QEMU for,
> bear in mind that successful execution of a program does not mean the
> program is free of illegal instructions.

Indeed. It only means that the execution trace is free of illegal instructions (in qemu's opinion).

> -----Original Message-----
> From: Petar Jovanovic [mailto:petar.jovanovic@rt-rk.com]
> Sent: 15 December 2014 14:59
> To: Daniel Sanders; Vasileios Kalintiris
> Cc: qemu-devel@nongnu.org; Leon Alrae
> Subject: RE: [PATCH] target-mips: add CPU definition for MIPS-II
> 
> Attempt to add a real model is for sure better option than adding a
> plain generic model.
> 
> As there will be a need to verify the support for MIPS2, we should aim
> for the platform that we can physically get at some point and use for
> testing/verification and improvement of the model. Untested support is
> not what you would benefit from, even if it is only for the sake of
> checking whether the instructions belong to MIPS2 set or not. Speaking
> of which, if that is the main purpose you would like to use QEMU for,
> bear in mind that successful execution of a program does not mean the
> program is free of illegal instructions.
> 
> Regards,
> Petar
> 
> From: Daniel Sanders [mailto:Daniel.Sanders@imgtec.com]
> Sent: Monday, December 15, 2014 3:03 PM
> To: Vasileios Kalintiris; Petar Jovanovic
> Cc: qemu-devel@nongnu.org; Leon Alrae
> Subject: RE: [PATCH] target-mips: add CPU definition for MIPS-II
> 
> Hi,
> 
> FWIW, the R6000 was a MIPS-II processor but I understand there was never a
> proper manual for it. http://www.linux-mips.org/wiki/R6000 has a small
> amount of information but not enough to accurately fill in qemu's structure.
> 
> > If this is really problematic for qemu, why don't we add an
> > --enable-experimental-targets, --enable-generic-targets or something
> > similar for generic/old CPU definitions?
> 
> One other possibility is to use a real CPU name such as R6000 but use
> reasonable guesses where information is unavailable. Is that a good
> compromise?
> 
> Daniel Sanders
> Leading Software Design Engineer, MIPS Processor IP
> Imagination Technologies Limited
> www.imgtec.com
> 
> From: Vasileios Kalintiris
> Sent: 15 December 2014 10:09
> To: Petar Jovanovic
> Cc: qemu-devel@nongnu.org; Leon Alrae; Daniel Sanders
> Subject: RE: [PATCH] target-mips: add CPU definition for MIPS-II
> 
> Hello Petar,
> 
> I've seen some older threads in the mailing list and I'm aware that
> adding generic CPU definitions is something that should be avoided.
> However, I don't have any real MIPS-II machine readily available at
> the moment.
> 
> We need support for the MIPS-II ISA because we enabled the MIPS-II
> target in the Clang/LLVM projects and we are running the LLVM
> test-suite under QEMU. This allows us to verify that we are not
> emitting invalid instructions or instructions that belong to another
> version of the ISA. Also, Debian targets MIPS-II for compatibility
> reasons and testing the code generation of the compiler for that ISA
> is rather important.
> 
> So there's an actual need for a MIPS-II definition and it wouldn't
> be convenient to have to maintain out-of-tree support for MIPS-II
> 
> If this is really problematic for qemu, why don't we add an
> --enable-experimental-targets, --enable-generic-targets or something
> similar for generic/old CPU definitions?
> 
> Thanks,
> Vasileios Kalintiris
> ________________________________________
> From: Petar Jovanovic [petar.jovanovic@rt-rk.com]
> Sent: 01 December 2014 23:45
> To: Vasileios Kalintiris
> Cc: qemu-devel@nongnu.org; Leon Alrae
> Subject: RE: [PATCH] target-mips: add CPU definition for MIPS-II
> Adding (another) generic model for an old ISA revision is rather
> discouraged in QEMU trunk. Can you add a particular real CPU model?
> 
> Regards,
> Petar
> ________________________________________
> From: Vasileios Kalintiris
> Sent: 25 November 2014 11:04
> To: address@hidden
> Cc: Leon Alrae; address@hidden
> Subject: [PATCH] target-mips: add CPU definition for MIPS-II
> 
> Add mips2-generic among CPU definitions for MIPS.
> 
> Signed-off-by: Vasileios Kalintiris <address@hidden>
> ---
> target-mips/translate_init.c | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
> 
> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> index 148b394..d4b1cd8 100644
> --- a/target-mips/translate_init.c
> +++ b/target-mips/translate_init.c
> @@ -108,6 +108,29 @@ struct mips_def_t {
> static const mips_def_t mips_defs[] =
> {
>      {
> +        /* A generic CPU providing MIPS-II features.
> +           FIXME: Eventually this should be replaced by a real CPU model.
> */
> +        .name = "mips2-generic",
> +        .CP0_PRid = 0x00018000,
> +        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
> +        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 <<
> CP0C1_MMU) |
> +                      (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
> +                      (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
> +                      (0 << CP0C1_CA),
> +        .CP0_Config2 = MIPS_CONFIG2,
> +        .CP0_Config3 = MIPS_CONFIG3,
> +        .CP0_LLAddr_rw_bitmask = 0,
> +        .CP0_LLAddr_shift = 4,
> +        .SYNCI_Step = 32,
> +        .CCRes = 2,
> +        .CP0_Status_rw_bitmask = 0x30000011,
> +        .CP1_fcr0 = (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S),
> +        .SEGBITS = 32,
> +        .PABITS = 32,
> +        .insn_flags = CPU_MIPS2,
> +        .mmu_type = MMU_TYPE_R4000,
> +    },
> +    {
>          .name = "4Kc",
>          .CP0_PRid = 0x00018000,
>          .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
> --
> 
> ping
> 

Re: [Qemu-devel] [PATCH] target-mips: add CPU definition for MIPS-II

[Leon Alrae]

Hi Daniel,

On 15/12/2014 14:03, Daniel Sanders wrote:
> Hi,
> 
>  
> 
> FWIW, the R6000 was a MIPS-II processor but I understand there was never
> a proper manual for it. http://www.linux-mips.org/wiki/R6000 has a small
> amount of information but not enough to accurately fill in qemu's structure.
> 
>  
> 
>> If this is really problematic for qemu, why don't we add an
>> --enable-experimental-targets, --enable-generic-targets or something
>> similar for generic/old CPU definitions?
> 
>  
> 
> One other possibility is to use a real CPU name such as R6000 but use
> reasonable guesses where information is unavailable. Is that a good
> compromise?

Adding R6000 sounds like the right way to go. Probably it won't be
accurately defined in QEMU until we can use the real hardware as a
reference, but this is still better than "MIPS-II generic CPU".

Thanks,
Leon

Re: [Qemu-devel] [PATCH] target-mips: add CPU definition for MIPS-II

[Maciej W. Rozycki]

On Tue, 25 Nov 2014, Vasileios Kalintiris wrote:

> Add mips2-generic among CPU definitions for MIPS.
> 
> Signed-off-by: Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com>
> ---
>  target-mips/translate_init.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> index 148b394..d4b1cd8 100644
> --- a/target-mips/translate_init.c
> +++ b/target-mips/translate_init.c
> @@ -108,6 +108,29 @@ struct mips_def_t {
>  static const mips_def_t mips_defs[] =
>  {
>      {
> +        /* A generic CPU providing MIPS-II features.
> +           FIXME: Eventually this should be replaced by a real CPU model. */

 Umm, this comment is wishful thinking I am afraid, getting a real MIPS II 
processor emulated, i.e. the R6000, will be quite a challenge.

 For one COP0 is completely different to anything else, in particular as 
far as the MMU and the cache are concerned.  Plus we don't know the 
opcodes for some instructions, e.g. the R6000-specific LD and SD 
operations, implemented analogously to LDC1 and SDC1; their opcodes might 
be just the same as MIPS III+ LD/SD (which should be safe for user 
software as in 32-bit user mode they'd trap on MIPS III+ processors such 
as the R4000, etc.), but I wouldn't bet on it.  Likewise all the cache 
maintenance instructions.

 To the best of my knowledge there wasn't any other plain MIPS II 
implementation that might be easier to emulate.  LSI's TinyRISC processors 
were close, but lacked the LL and SC instructions (TR4101 didn't have SYNC 
either).  OTOH they had the MIPS16 ASE implemented; the original version 
that is of course, i.e. no compact jumps, SAVE/RESTORE, etc.  They had no 
FPU either -- a COP1 interface was available and an FPU chip apparently 
planned, but never implemented.

 All the other 32-bit pieces of the era were AFAIK more of MIPS I than 
MIPS II implementations.  That in particular includes IDT and Toshiba 
gear.  Maybe I have missed something and someone can speak out who knows 
better what was available around mid 1990s though.

> +        .name = "mips2-generic",
> +        .CP0_PRid = 0x00018000,

 You need to set CP0.PRId such that CompanyID is 0, meaning a legacy 
processor, or otherwise software will become confused.  In the R6000 the 
actual value was, according to Linux sources, 0x00000300, the same as in 
the R3000A.  I am not actually sure how the two quite different processors 
could be told apart, perhaps poking at another CP0 register would do.

> +        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
> +        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
> +                      (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
> +                      (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
> +                      (0 << CP0C1_CA),
> +        .CP0_Config2 = MIPS_CONFIG2,
> +        .CP0_Config3 = MIPS_CONFIG3,

 Likewise, these aren't right, there were no CP0 Config registers on the 
R6000, the cache subsystem was completely different.  I realise some of 
these bits are fake for internal use, but the rest should best be cleared, 
they can only confuse the reader.

> +        .CP0_LLAddr_rw_bitmask = 0,
> +        .CP0_LLAddr_shift = 4,
> +        .SYNCI_Step = 32,
> +        .CCRes = 2,
> +        .CP0_Status_rw_bitmask = 0x30000011,
> +        .CP1_fcr0 = (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S),

 This isn't right, for a MIPS II processor CP1.FIR will have these bits 
clear and the Implementation/Revision fields set to a non-zero value to 
let software probe for the presence of the FPU.

> +        .SEGBITS = 32,
> +        .PABITS = 32,
> +        .insn_flags = CPU_MIPS2,
> +        .mmu_type = MMU_TYPE_R4000,
> +    },

 Yeah, as I say the MMU type isn't really right.  Mind that these 
processors used RFE rather than ERET for exception return too, to reflect 
a different exception model (the same as with MIPS I) and consequently 
layout of the CP0.Status register; all of which to be taken into account 
for a MIPS II processor as well.

 What do you really need this processor template for and how do you 
propose to use it?  Is it worth including one upstream that diverges so 
much from what the actual processor was like?  Is it for the user 
emulation mode only?

  Maciej