From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Gn2Wo-0000P2-Ol for qemu-devel@nongnu.org; Wed, 22 Nov 2006 19:33:22 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Gn2Wn-0000OX-Q1 for qemu-devel@nongnu.org; Wed, 22 Nov 2006 19:33:22 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Gn2Wn-0000OQ-Ij for qemu-devel@nongnu.org; Wed, 22 Nov 2006 19:33:21 -0500 Received: from [212.78.202.65] (helo=lmfilto01.st1.spray.net) by monty-python.gnu.org with esmtp (Exim 4.52) id 1Gn2Wn-0002te-4h for qemu-devel@nongnu.org; Wed, 22 Nov 2006 19:33:21 -0500 Received: from lmfilto01.st1.spray.net (localhost [127.0.0.1]) by lmfilto01-10027.st1.spray.net (Postfix) with ESMTP id 65516B6F583 for ; Wed, 22 Nov 2006 21:18:48 +0000 (GMT) Received: from localhost (localhost [127.0.0.1]) by lmfilto01-10025.st1.spray.net (Postfix) with ESMTP id 81326B8335D for ; Wed, 22 Nov 2006 21:12:57 +0000 (GMT) Received: from ttlaptop (unknown [84.219.16.41]) by lmsmtp01.st1.spray.net (Postfix) with ESMTP id 05C7D1C14 for ; Wed, 22 Nov 2006 21:12:56 +0000 (GMT) From: =?iso-8859-1?Q?Torbj=F6rn_Andersson?= Subject: SV: [Qemu-devel] ARM CPSR and conditional instructions Date: Wed, 22 Nov 2006 22:13:01 +0100 Message-ID: <004801c70e7a$fe63a290$3101a8c0@ttlaptop> MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_NextPart_000_0049_01C70E83.60280A90" In-Reply-To: <000601c70db2$4bead750$3101a8c0@ttlaptop> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. ------=_NextPart_000_0049_01C70E83.60280A90 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable I=92m sorry for spamming you mailing list with my duplicate posts. I had = some problems sending my mail.=20 =20 /Torbj=F6rn _____ =20 Fr=E5n: qemu-devel-bounces+tobbe.tt_home.se=3Dspray.se@nongnu.org [mailto:qemu-devel-bounces+tobbe.tt_home.se=3Dspray.se@nongnu.org] F=F6r Torbj=F6rn Andersson Skickat: den 21 november 2006 22:16 Till: qemu-devel@nongnu.org =C4mne: [Qemu-devel] ARM CPSR and conditional instructions =20 Hello qemu developers! I=B4m using QEMU for some ARM debugging and I have som questions = regardning the CPSR register. I get the feeling that the CPSR condition code bits, representing the results from the ALU, are not maintained at all points. = Is the JIT in QEMU tailored in any way towards GCC output? (Resulting in = issues with the output of other compilers that make use of the conditional execution of instructions etc.) What I want to do is to try to verify QEMU maintains the CPSR register = and if not fix it. However, it is not trivial identify where the updates = should be placed. The relationship between translate.c and op.c is not trival I must say :) I would be happy I anyone here could give me some pointers on how the updates of the CPSR register is done today and what the strategy is. I = guess there are plenty of performance ideas here as in the rest of qemu. Does anyone have any reflection on this topic or can anyone give me some pointers? Torbj=F6rn =20 ------=_NextPart_000_0049_01C70E83.60280A90 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

I’m sorry = for spamming you mailing list with my duplicate posts. I had some problems sending my = mail.

=

/Torbj=F6rn<= /o:p>

Fr=E5n: qemu-devel-bounces+tobbe.tt_home.se=3Dspray.se@nongnu.org [mailto:qemu-devel-bounces+tobbe.tt_home.se=3Dspray.se@nongnu.org] = F=F6r Torbj=F6rn = Andersson
Skickat: den 21 november = 2006 22:16
Till: qemu-devel@nongnu.org
=C4mne: [Qemu-devel] ARM = CPSR and conditional instructions

Hello qemu developers!

I=B4m using QEMU for some ARM debugging and I have som questions = regardning the CPSR register. I get the feeling that the CPSR condition code bits, = representing the results from the ALU, are not maintained at all points. Is the JIT = in QEMU tailored in any way towards GCC output? (Resulting in issues with the = output of other compilers that make use of the conditional execution of = instructions etc.)

What I want to do is to try to verify QEMU maintains the CPSR register = and if not fix it. However, it is not trivial identify where the updates should = be placed. The relationship between translate.c and op.c is not trival I = must say :)

I would be happy I anyone here could give me = some pointers on how the updates of the CPSR register is done today and what = the strategy is. I guess there are plenty of performance ideas here as in = the rest of qemu.

Does anyone have any reflection on this topic or can anyone give me some pointers?

Torbj=F6rn

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