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From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Fan Ni <fan.ni@samsung.com>
Subject: [PULL 61/63] hw/cxl: Add tunneled command support to mailbox for switch cci.
Date: Tue, 7 Nov 2023 05:13:55 -0500	[thread overview]
Message-ID: <004e3a93b814ca2d13ee2feb1f9ebacef6c83b9e.1699351720.git.mst@redhat.com> (raw)
In-Reply-To: <cover.1699351720.git.mst@redhat.com>

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

This implementation of tunneling makes the choice that our Type 3 device is
a Logical Device (LD) of a Multi-Logical Device (MLD) that just happens to
only have one LD for now.

Tunneling is supported from a Switch Mailbox CCI (and shortly via MCTP over
I2C connected to the switch MCTP CCI) via an outer level to the FM owned LD
in the MLD Type 3 device. From there an inner tunnel may be used to access
particular LDs.

Protocol wise, the following is what happens in a real system but we
don't emulate the transports - just the destinations and the payloads.

( Host -> Switch Mailbox CCI - in band FM-API mailbox command
  or
  Host -> Switch MCTP CCI - MCTP over I2C using the CXL FM-API
  MCTP Binding.
)
then (if a tunnel command)
Switch -> Type 3 FM Owned LD - MCTP over PCI VDM using the
CXL FM-API binding (addressed by switch port)
then (if unwrapped command also a tunnel command)
Type 3 FM Owned LD to LD0 via internal transport
(addressed by LD number)

or (added shortly)

Host to Type 3 FM Owned MCTP CCI - MCTP over I2C using the
CXL FM-API MCTP Binding.
then (if unwrapped comand is a tunnel comamnd)
Type 3 FM Owned LD to LD0 via internal transport.
(addressed by LD number)

It is worth noting that the tunneling commands over PCI VDM
presumably use the appropriate MCTP binding depending on opcode.
This may be the CXL FMAPI binding or the CXL Memory Device Binding.

Additional commands will need to be added to make this
useful beyond testing the tunneling works.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Message-Id: <20231023160806.13206-18-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/cxl/cxl_device.h |   9 ++
 hw/cxl/cxl-mailbox-utils.c  | 162 ++++++++++++++++++++++++++++++++++++
 hw/mem/cxl_type3.c          |  11 +++
 3 files changed, 182 insertions(+)

diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 70aca9024c..61b7f897f7 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -279,6 +279,12 @@ int cxl_process_cci_message(CXLCCI *cci, uint8_t set, uint8_t cmd,
                             size_t len_in, uint8_t *pl_in,
                             size_t *len_out, uint8_t *pl_out,
                             bool *bg_started);
+void cxl_initialize_t3_fm_owned_ld_mctpcci(CXLCCI *cci, DeviceState *d,
+                                           DeviceState *intf,
+                                           size_t payload_max);
+
+void cxl_initialize_t3_ld_cci(CXLCCI *cci, DeviceState *d,
+                              DeviceState *intf, size_t payload_max);
 
 #define cxl_device_cap_init(dstate, reg, cap_id, ver)                      \
     do {                                                                   \
@@ -397,6 +403,9 @@ struct CXLType3Dev {
     CXLComponentState cxl_cstate;
     CXLDeviceState cxl_dstate;
     CXLCCI cci; /* Primary PCI mailbox CCI */
+    /* Always intialized as no way to know if a VDM might show up */
+    CXLCCI vdm_fm_owned_ld_mctp_cci;
+    CXLCCI ld0_cci;
 
     /* DOE */
     DOECap doe_cdat;
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 693c2cbdcd..b365575097 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -82,8 +82,132 @@ enum {
     PHYSICAL_SWITCH = 0x51,
         #define IDENTIFY_SWITCH_DEVICE      0x0
         #define GET_PHYSICAL_PORT_STATE     0x1
+    TUNNEL = 0x53,
+        #define MANAGEMENT_COMMAND     0x0
 };
 
+/* CCI Message Format CXL r3.0 Figure 7-19 */
+typedef struct CXLCCIMessage {
+    uint8_t category;
+#define CXL_CCI_CAT_REQ 0
+#define CXL_CCI_CAT_RSP 1
+    uint8_t tag;
+    uint8_t resv1;
+    uint8_t command;
+    uint8_t command_set;
+    uint8_t pl_length[3];
+    uint16_t rc;
+    uint16_t vendor_specific;
+    uint8_t payload[];
+} QEMU_PACKED CXLCCIMessage;
+
+/* This command is only defined to an MLD FM Owned LD or an MHD */
+static CXLRetCode cmd_tunnel_management_cmd(const struct cxl_cmd *cmd,
+                                            uint8_t *payload_in,
+                                            size_t len_in,
+                                            uint8_t *payload_out,
+                                            size_t *len_out,
+                                            CXLCCI *cci)
+{
+    PCIDevice *tunnel_target;
+    CXLCCI *target_cci;
+    struct {
+        uint8_t port_or_ld_id;
+        uint8_t target_type;
+        uint16_t size;
+        CXLCCIMessage ccimessage;
+    } QEMU_PACKED *in;
+    struct {
+        uint16_t resp_len;
+        uint8_t resv[2];
+        CXLCCIMessage ccimessage;
+    } QEMU_PACKED *out;
+    size_t pl_length, length_out;
+    bool bg_started;
+    int rc;
+
+    if (cmd->in < sizeof(*in)) {
+        return CXL_MBOX_INVALID_INPUT;
+    }
+    in = (void *)payload_in;
+    out = (void *)payload_out;
+
+    /* Enough room for minimum sized message - no payload */
+    if (in->size < sizeof(in->ccimessage)) {
+        return CXL_MBOX_INVALID_PAYLOAD_LENGTH;
+    }
+    /* Length of input payload should be in->size + a wrapping tunnel header */
+    if (in->size != len_in - offsetof(typeof(*out), ccimessage)) {
+        return CXL_MBOX_INVALID_PAYLOAD_LENGTH;
+    }
+    if (in->ccimessage.category != CXL_CCI_CAT_REQ) {
+        return CXL_MBOX_INVALID_INPUT;
+    }
+
+    if (in->target_type != 0) {
+        qemu_log_mask(LOG_UNIMP,
+                      "Tunneled Command sent to non existent FM-LD");
+        return CXL_MBOX_INVALID_INPUT;
+    }
+
+    /*
+     * Target of a tunnel unfortunately depends on type of CCI readint
+     * the message.
+     * If in a switch, then it's the port number.
+     * If in an MLD it is the ld number.
+     * If in an MHD target type indicate where we are going.
+     */
+    if (object_dynamic_cast(OBJECT(cci->d), TYPE_CXL_TYPE3)) {
+        CXLType3Dev *ct3d = CXL_TYPE3(cci->d);
+        if (in->port_or_ld_id != 0) {
+            /* Only pretending to have one for now! */
+            return CXL_MBOX_INVALID_INPUT;
+        }
+        target_cci = &ct3d->ld0_cci;
+    } else if (object_dynamic_cast(OBJECT(cci->d), TYPE_CXL_USP)) {
+        CXLUpstreamPort *usp = CXL_USP(cci->d);
+
+        tunnel_target = pcie_find_port_by_pn(&PCI_BRIDGE(usp)->sec_bus,
+                                             in->port_or_ld_id);
+        if (!tunnel_target) {
+            return CXL_MBOX_INVALID_INPUT;
+        }
+        tunnel_target =
+            pci_bridge_get_sec_bus(PCI_BRIDGE(tunnel_target))->devices[0];
+        if (!tunnel_target) {
+            return CXL_MBOX_INVALID_INPUT;
+        }
+        if (object_dynamic_cast(OBJECT(tunnel_target), TYPE_CXL_TYPE3)) {
+            CXLType3Dev *ct3d = CXL_TYPE3(tunnel_target);
+            /* Tunneled VDMs always land on FM Owned LD */
+            target_cci = &ct3d->vdm_fm_owned_ld_mctp_cci;
+        } else {
+            return CXL_MBOX_INVALID_INPUT;
+        }
+    } else {
+        return CXL_MBOX_INVALID_INPUT;
+    }
+
+    pl_length = in->ccimessage.pl_length[2] << 16 |
+        in->ccimessage.pl_length[1] << 8 | in->ccimessage.pl_length[0];
+    rc = cxl_process_cci_message(target_cci,
+                                 in->ccimessage.command_set,
+                                 in->ccimessage.command,
+                                 pl_length, in->ccimessage.payload,
+                                 &length_out, out->ccimessage.payload,
+                                 &bg_started);
+    /* Payload should be in place. Rest of CCI header and needs filling */
+    out->resp_len = length_out + sizeof(CXLCCIMessage);
+    st24_le_p(out->ccimessage.pl_length, length_out);
+    out->ccimessage.rc = rc;
+    out->ccimessage.category = CXL_CCI_CAT_RSP;
+    out->ccimessage.command = in->ccimessage.command;
+    out->ccimessage.command_set = in->ccimessage.command_set;
+    out->ccimessage.tag = in->ccimessage.tag;
+    *len_out = length_out + sizeof(*out);
+
+    return CXL_MBOX_SUCCESS;
+}
 
 static CXLRetCode cmd_events_get_records(const struct cxl_cmd *cmd,
                                          uint8_t *payload_in, size_t len_in,
@@ -1171,6 +1295,8 @@ static const struct cxl_cmd cxl_cmd_set_sw[256][256] = {
         cmd_identify_switch_device, 0, 0 },
     [PHYSICAL_SWITCH][GET_PHYSICAL_PORT_STATE] = { "SWITCH_PHYSICAL_PORT_STATS",
         cmd_get_physical_port_state, ~0, 0 },
+    [TUNNEL][MANAGEMENT_COMMAND] = { "TUNNEL_MANAGEMENT_COMMAND",
+                                     cmd_tunnel_management_cmd, ~0, 0 },
 };
 
 /*
@@ -1347,3 +1473,39 @@ void cxl_initialize_mailbox_t3(CXLCCI *cci, DeviceState *d, size_t payload_max)
     cci->intf = d;
     cxl_init_cci(cci, payload_max);
 }
+
+static const struct cxl_cmd cxl_cmd_set_t3_ld[256][256] = {
+    [INFOSTAT][IS_IDENTIFY] = { "IDENTIFY", cmd_infostat_identify, 0, 0 },
+    [LOGS][GET_SUPPORTED] = { "LOGS_GET_SUPPORTED", cmd_logs_get_supported, 0,
+                              0 },
+    [LOGS][GET_LOG] = { "LOGS_GET_LOG", cmd_logs_get_log, 0x18, 0 },
+};
+
+void cxl_initialize_t3_ld_cci(CXLCCI *cci, DeviceState *d, DeviceState *intf,
+                               size_t payload_max)
+{
+    cci->cxl_cmd_set = cxl_cmd_set_t3_ld;
+    cci->d = d;
+    cci->intf = intf;
+    cxl_init_cci(cci, payload_max);
+}
+
+static const struct cxl_cmd cxl_cmd_set_t3_fm_owned_ld_mctp[256][256] = {
+    [INFOSTAT][IS_IDENTIFY] = { "IDENTIFY", cmd_infostat_identify, 0,  0},
+    [LOGS][GET_SUPPORTED] = { "LOGS_GET_SUPPORTED", cmd_logs_get_supported, 0,
+                              0 },
+    [LOGS][GET_LOG] = { "LOGS_GET_LOG", cmd_logs_get_log, 0x18, 0 },
+    [TIMESTAMP][GET] = { "TIMESTAMP_GET", cmd_timestamp_get, 0, 0 },
+    [TUNNEL][MANAGEMENT_COMMAND] = { "TUNNEL_MANAGEMENT_COMMAND",
+                                     cmd_tunnel_management_cmd, ~0, 0 },
+};
+
+void cxl_initialize_t3_fm_owned_ld_mctpcci(CXLCCI *cci, DeviceState *d,
+                                           DeviceState *intf,
+                                           size_t payload_max)
+{
+    cci->cxl_cmd_set = cxl_cmd_set_t3_fm_owned_ld_mctp;
+    cci->d = d;
+    cci->intf = intf;
+    cxl_init_cci(cci, payload_max);
+}
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index a766c64575..52647b4ac7 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -936,6 +936,17 @@ static void ct3d_reset(DeviceState *dev)
 
     cxl_component_register_init_common(reg_state, write_msk, CXL2_TYPE3_DEVICE);
     cxl_device_register_init_t3(ct3d);
+
+    /*
+     * Bring up an endpoint to target with MCTP over VDM.
+     * This device is emulating an MLD with single LD for now.
+     */
+    cxl_initialize_t3_fm_owned_ld_mctpcci(&ct3d->vdm_fm_owned_ld_mctp_cci,
+                                          DEVICE(ct3d), DEVICE(ct3d),
+                                          512); /* Max payload made up */
+    cxl_initialize_t3_ld_cci(&ct3d->ld0_cci, DEVICE(ct3d), DEVICE(ct3d),
+                             512); /* Max payload made up */
+
 }
 
 static Property ct3_props[] = {
-- 
MST



  parent reply	other threads:[~2023-11-07 10:24 UTC|newest]

Thread overview: 73+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-07 10:09 [PULL 00/63] virtio,pc,pci: features, fixes Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 01/63] vhost-user.rst: Improve [GS]ET_VRING_BASE doc Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 02/63] vhost-user.rst: Clarify enabling/disabling vrings Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 03/63] vhost-user.rst: Introduce suspended state Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 04/63] vhost-user.rst: Migrating back-end-internal state Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 05/63] vhost-user: Interface for migration state transfer Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 06/63] vhost: Add high-level state save/load functions Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 07/63] vhost-user-fs: Implement internal migration Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 08/63] Add virtio-sound device stub Michael S. Tsirkin
2023-11-09 14:30   ` Peter Maydell
2023-11-09 15:50     ` Manos Pitsidianakis
2023-11-09 16:06       ` Peter Maydell
2023-11-09 16:10       ` Alex Bennée
2023-11-07 10:10 ` [PULL 09/63] Add virtio-sound-pci device Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 10/63] virtio-sound: handle control messages and streams Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 11/63] virtio-sound: handle VIRTIO_SND_R_PCM_INFO request Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 12/63] virtio-sound: handle VIRTIO_SND_R_PCM_{START,STOP} Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 13/63] virtio-sound: handle VIRTIO_SND_R_PCM_SET_PARAMS Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 14/63] virtio-sound: handle VIRTIO_SND_R_PCM_PREPARE Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 15/63] virtio-sound: handle VIRTIO_SND_R_PCM_RELEASE Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 16/63] virtio-sound: implement audio output (TX) Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 17/63] virtio-sound: implement audio capture (RX) Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 18/63] docs/system: add basic virtio-snd documentation Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 19/63] vdpa: Restore hash calculation state Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 20/63] vdpa: Allow VIRTIO_NET_F_HASH_REPORT in SVQ Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 21/63] vdpa: Add SetSteeringEBPF method for NetClientState Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 22/63] vdpa: Restore receive-side scaling state Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 23/63] vdpa: Allow VIRTIO_NET_F_RSS in SVQ Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 24/63] tests: test-smp-parse: Add the test for cores/threads per socket helpers Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 25/63] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 count test Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 26/63] tests: bios-tables-test: Add test for smbios type4 count Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 27/63] tests: bios-tables-test: Add ACPI table binaries for smbios type4 count test Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 28/63] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core " Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 29/63] tests: bios-tables-test: Add test for smbios type4 core count Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 30/63] tests: bios-tables-test: Add ACPI table binaries for smbios type4 core count test Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 31/63] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core count2 test Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 32/63] tests: bios-tables-test: Extend smbios core count2 test to cover general topology Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 33/63] tests: bios-tables-test: Update ACPI table binaries for smbios core count2 test Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 34/63] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count test Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 35/63] tests: bios-tables-test: Add test for smbios type4 thread count Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 36/63] tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count test Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 37/63] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count2 test Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 38/63] tests: bios-tables-test: Add test for smbios type4 thread count2 Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 39/63] tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count2 test Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 40/63] hw/cxl: Use a switch to explicitly check size in caps_reg_read() Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 41/63] hw/cxl: Use switch statements for read and write of cachemem registers Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 42/63] hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 43/63] hw/cxl: Line length reductions Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 44/63] hw/cxl: Fix a QEMU_BUILD_BUG_ON() in switch statement scope issue Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 45/63] hw/cxl/mbox: Pull the payload out of struct cxl_cmd and make instances constant Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 46/63] hw/cxl/mbox: Split mailbox command payload into separate input and output Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 47/63] hw/cxl/mbox: Pull the CCI definition out of the CXLDeviceState Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 48/63] hw/cxl/mbox: Generalize the CCI command processing Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 49/63] hw/pci-bridge/cxl_upstream: Move defintion of device to header Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 50/63] hw/cxl: Add a switch mailbox CCI function Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 51/63] hw/cxl/mbox: Add Information and Status / Identify command Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 52/63] hw/cxl/mbox: Add Physical Switch " Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 53/63] hw/pci-bridge/cxl_downstream: Set default link width and link speed Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 54/63] hw/cxl: Implement Physical Ports status retrieval Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 55/63] hw/cxl/mbox: Add support for background operations Michael S. Tsirkin
2023-11-09 14:44   ` Peter Maydell
2023-11-10  4:25     ` Davidlohr Bueso
2023-11-07 10:13 ` [PULL 56/63] hw/cxl/mbox: Wire up interrupts for background completion Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 57/63] hw/cxl: Add support for device sanitation Michael S. Tsirkin
2023-11-09 14:39   ` Peter Maydell
2023-11-10  4:14     ` Davidlohr Bueso
2023-11-07 10:13 ` [PULL 58/63] hw/cxl/mbox: Add Get Background Operation Status Command Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 59/63] hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 60/63] hw/cxl: Add dummy security state get Michael S. Tsirkin
2023-11-07 10:13 ` Michael S. Tsirkin [this message]
2023-11-07 10:13 ` [PULL 62/63] acpi/tests/avocado/bits: enforce 32-bit SMBIOS entry point Michael S. Tsirkin
2023-11-07 10:14 ` [PULL 63/63] acpi/tests/avocado/bits: enable console logging from bits VM Michael S. Tsirkin
2023-11-07 13:40 ` [PULL 00/63] virtio,pc,pci: features, fixes Stefan Hajnoczi

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