Re: [PATCH] target/riscv: fix ctzw behavior

[Richard Henderson <richard.henderson@linaro.org>]

On 2/3/23 04:00, Vladimir Isaev wrote:
> According to spec, ctzw should work with 32-bit register, not 64.
> 
> For example, previous implementation returns 33 for (1<<33) input
> when the new one returns 32.
> 
> Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
> ---
>   target/riscv/insn_trans/trans_rvb.c.inc | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index e2b8329f1e5b..42c6ded13de8 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -80,7 +80,14 @@ static void gen_ctz(TCGv ret, TCGv arg1)
>   
>   static void gen_ctzw(TCGv ret, TCGv arg1)
>   {
> -    tcg_gen_ctzi_tl(ret, arg1, 32);
> +    TCGv_i32 t = tcg_temp_new_i32();
> +
> +    tcg_gen_trunc_tl_i32(t, arg1);
> +    tcg_gen_ctzi_i32(t, t, 32);
> +
> +    tcg_gen_extu_i32_tl(ret, t);
> +
> +    tcg_temp_free_i32(t);

This was supposed to be handled by EXT_ZERO in gen_unary.
Looks like trans_ctzw is missing

     ctx->ol = MXL_RV32;

similar to trans_ctpopw just below.


r~