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From: "Jeebs" <jeebs@yango.us>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] x86_64 target
Date: Wed, 5 Jan 2005 11:48:13 -0600	[thread overview]
Message-ID: <008001c4f34e$be22b200$ad4aa50c@computername> (raw)
In-Reply-To: 200501041429.51792.paul@codesourcery.com

From: "Paul Brook"

> On Tuesday 04 January 2005 02:15, Karl Magdsick wrote:
>> The EMT Xeons implement all of the amd64 instructions that were in an
>> early release of the instruction set reference, so I think a single
> 
> The Intel chips actually implement all the instructions except 3DNOW and add 
> SSE3, same as p4 vs. AthlonXP. These are the only instruction set 
> differences, and the only differences that are visible from userspace.

Actually, I thought the Intel chips did *not* implement the full x86-64 instruction set.  That's what a few early reports were saying.

They made their 64 bit version using a draft of the initial 64 bit specs, but AMD made some changes right at the end, and as a result the Intel chips (and AMD's own initial batch of chips) don't fully support the x86-64 instruction set.

I haven't been keeping track, but I haven't heard of any changes from Intel to implement the missing instruction(s).

  reply	other threads:[~2005-01-05 18:00 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2005-01-04  0:18 [Qemu-devel] x86_64 target Fabrice Bellard
2005-01-04  2:15 ` Karl Magdsick
2005-01-04 14:29   ` Paul Brook
2005-01-05 17:48     ` Jeebs [this message]
2005-01-04  6:31 ` [Qemu-devel] " Alexander E. Patrakov
2005-01-04 19:56   ` Fabrice Bellard
2005-01-06 12:10 ` [Qemu-devel] " Lennert Buytenhek
2005-01-06 12:42   ` Lennert Buytenhek
2005-01-17 17:54     ` [Qemu-devel] " Ronald

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