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Tue, 17 Aug 2021 08:39:04 -0700 (PDT) Received: from [192.168.3.43] ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id nr6sm2537820pjb.39.2021.08.17.08.39.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Aug 2021 08:39:03 -0700 (PDT) Subject: Re: [PULL 24/27] accel/tcg: Move breakpoint recognition outside translation To: Peter Maydell References: <20210721195954.879535-1-richard.henderson@linaro.org> <20210721195954.879535-25-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <00aaafa2-74dd-3c19-1d47-93bc2fc0d83c@linaro.org> Date: Tue, 17 Aug 2021 05:39:00 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.961, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?Q?Alex_Benn=c3=a9e?= , Mark Cave-Ayland , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/17/21 3:33 AM, Peter Maydell wrote: > On Wed, 21 Jul 2021 at 21:00, Richard Henderson > wrote: >> >> Trigger breakpoints before beginning translation of a TB >> that would begin with a BP. Thus we never generate code >> for the BP at all. > > I happened to notice in the Arm ARM today a corner case that this > implementation approach I think gets wrong: the priority ordering > of exceptions is supposed to be (among others) > * (architectural) software step > * instruction abort > * (architectural) breakpoints > > I think that doing the bp check here means it is incorrectly > hoisted up the priority order above both swstep and insn > abort. Hmm, you're correct that we get this wrong. > We probably didn't do these in the right priority > order before this series, though, and I dunno whether > we get the insn-abort vs swstep ordering right either... And you're correct that we got it wrong beforehand. The reorg did not alter the recognized ordering of the exceptions. I'm a bit surprised that insn-abort comes higher than breakpoint. Fixing this would mean performing the insn decode and only then recognizing the breakpoint. One of the intermediate versions of the patch set would have allowed this sort of thing, but I didn't realize it was necessary. And it would be a huge job to alter all of the trans_* functions. Fixing the order of swstep and bp can be done via the arm_debug_check_breakpoint hook. Just return false if swstep is enabled. r~