From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51398) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxAui-0007SJ-Dd for qemu-devel@nongnu.org; Tue, 26 May 2015 05:12:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YxAud-0003xT-EN for qemu-devel@nongnu.org; Tue, 26 May 2015 05:12:44 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:18419) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxAud-0003x9-87 for qemu-devel@nongnu.org; Tue, 26 May 2015 05:12:39 -0400 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NOY00CIM9KZAV90@mailout2.w1.samsung.com> for qemu-devel@nongnu.org; Tue, 26 May 2015 10:12:35 +0100 (BST) From: Pavel Fedin Date: Tue, 26 May 2015 12:12:34 +0300 Message-id: <00f901d09794$1ac0eeb0$5042cc10$@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7bit Content-language: ru Subject: [Qemu-devel] Proper PIDR values ??? List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: 'Shlomo Pongratz' , 'Eric Auger' , qemu-devel@nongnu.org, shlomopongratz@gmail.com Cc: 'Peter Maydell' , 'Christoffer Dall' Hello! > The value is taken from the gic-500 document in the re-distributer's table (3-7). > I don't know where the value 0x91 comes from as GICD_PIDR0 is 0x92, GICR_PIDR0 is 0x93 and > GITS_PIDR0 is 0x94. > In the GICv3 document section 5.4.21 it is also been written: > 0xFFE0 GICR_PIDR0 Bits [7:0]. Bits [7:0] of the ARM-defined DevID field. This field is 0x93 in > ARM implementations of a GICv3 or later Re-distributor. Hm, very interesting... Actually i still don't have architecture reference manual for GICv3. It's too slow and problematic to request it in a big company because of bureaucracy issues. :) So try to get around with: a) Linux source code. b) GIC-500 tech reference manual (from ARM InfoCenter) c) Hardware manual for my board (which seems to contain a part from arch manual, with all registers described). It's also under NDA, so i can't quote too much :) The doc (c) has this table regarding PIDR0[7:0] values for various things: --- cut --- PCC PIDR Part Number 0 Enumeration PCC_PIDR_PARTNUM0_E 0x0 NONE Reserved. 0x1 GICR GIC redistributor. 0x2 GICD GIC distributor. 0x3 GITS GIC ITS. 0x4 GTI_BZ GTI base. 0x5 GTI_CC GTI counter control. 0x6 GTI_CTL GTI control. 0x7 GTI_RD GTI counter read. 0x8 GTI_WC GTI watchdog control. --- cut --- Linaro guys (Peter, Eric, Christoffer, anyone), please judge us, who is correct? Kind regards, Pavel Fedin Expert Engineer Samsung Electronics Research center Russia