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envelope-from=ltaylorsimpson@gmail.com; helo=mail-qv1-xf2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org > -----Original Message----- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.cain@oss.qualcomm.com; richard.henderson@linaro.org; > philmd@linaro.org; quic_mathbern@quicinc.com; ale@rev.ng; anjo@rev.ng; > quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com; > alex.bennee@linaro.org; quic_mburton@quicinc.com; > sidneym@quicinc.com; Brian Cain ; Michael Lambert > > Subject: [PATCH 34/38] target/hexagon: Add initial MMU model >=20 > From: Brian Cain >=20 > Co-authored-by: Taylor Simpson > Co-authored-by: Michael Lambert > Co-authored-by: Sid Manning > Co-authored-by: Matheus Tavares Bernardino > > Signed-off-by: Brian Cain > diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c new > file mode 100644 index 0000000000..54c4ba2dbf > --- /dev/null > +++ b/target/hexagon/hex_mmu.c > @@ -0,0 +1,528 @@ > +/* > + * Copyright(c) 2019-2025 Qualcomm Innovation Center, Inc. All Rights > Reserved. > + * > + * SPDX-License-Identifier: GPL-2.0-or-later */ > + > +#include "qemu/osdep.h" > +#include "qemu/main-loop.h" > +#include "qemu/qemu-print.h" > +#include "cpu.h" > +#include "system/cpus.h" > +#include "internal.h" > +#include "exec/exec-all.h" > +#include "hex_mmu.h" > +#include "macros.h" > +#include "sys_macros.h" > +#include "reg_fields.h" > + > +#define GET_TLB_FIELD(ENTRY, FIELD) \ > + ((uint64_t)fEXTRACTU_BITS(ENTRY, reg_field_info[FIELD].width, \ > + reg_field_info[FIELD].offset)) > + > +/* PPD (physical page descriptor) */ > +static inline uint64_t GET_PPD(uint64_t entry) { > + return GET_TLB_FIELD(entry, PTE_PPD) | > + (GET_TLB_FIELD(entry, PTE_PA35) << > +reg_field_info[PTE_PPD].width); } > + > +#define NO_ASID (1 << 8) > + > +typedef enum { > + PGSIZE_4K, > + PGSIZE_16K, > + PGSIZE_64K, > + PGSIZE_256K, > + PGSIZE_1M, > + PGSIZE_4M, > + PGSIZE_16M, > + PGSIZE_64M, > + PGSIZE_256M, > + PGSIZE_1G, > + NUM_PGSIZE_TYPES > +} tlb_pgsize_t; > + > +static const char *pgsize_str[NUM_PGSIZE_TYPES] =3D { > + "4K", > + "16K", > + "64K", > + "256K", > + "1M", > + "4M", > + "16M", > + "64M", > + "256M", > + "1G", > +}; > + > +#define INVALID_MASK 0xffffffffLL > + > +static const uint64_t encmask_2_mask[] =3D { > + 0x0fffLL, /* 4k, 0000 */ > + 0x3fffLL, /* 16k, 0001 */ > + 0xffffLL, /* 64k, 0010 */ > + 0x3ffffLL, /* 256k, 0011 */ > + 0xfffffLL, /* 1m, 0100 */ > + 0x3fffffLL, /* 4m, 0101 */ > + 0xffffffLL, /* 16m, 0110 */ > + 0x3ffffffLL, /* 64m, 0111 */ > + 0xfffffffLL, /* 256m, 1000 */ > + 0x3fffffffLL, /* 1g, 1001 */ > + INVALID_MASK, /* RSVD, 0111 */ > +}; > + > +/* > + * @return the page size type from @a entry. > + */ > +static inline tlb_pgsize_t hex_tlb_pgsize_type(uint64_t entry) { > + if (entry =3D=3D 0) { > + qemu_log_mask(CPU_LOG_MMU, "%s: Supplied TLB entry was 0!\n", > __func__); > + return 0; > + } > + tlb_pgsize_t size =3D ctz64(entry); > + g_assert(size < NUM_PGSIZE_TYPES); > + return size; > +} > + > +/* > + * @return the page size of @a entry, in bytes. > + */ > +static inline uint64_t hex_tlb_page_size_bytes(uint64_t entry) { > + return 1ull << (TARGET_PAGE_BITS + 2 * = hex_tlb_pgsize_type(entry)); > +} > + > +static inline uint64_t hex_tlb_phys_page_num(uint64_t entry) { > + uint32_t ppd =3D GET_PPD(entry); > + return ppd >> 1; > +} > + > +static inline uint64_t hex_tlb_phys_addr(uint64_t entry) { > + uint64_t pagemask =3D encmask_2_mask[hex_tlb_pgsize_type(entry)]; > + uint64_t pagenum =3D hex_tlb_phys_page_num(entry); > + uint64_t PA =3D (pagenum << TARGET_PAGE_BITS) & (~pagemask); > + return PA; > +} > + > +static inline uint64_t hex_tlb_virt_addr(uint64_t entry) { > + return (uint64_t)GET_TLB_FIELD(entry, PTE_VPN) << > TARGET_PAGE_BITS; > +} > + > +static bool hex_dump_mmu_entry(FILE *f, uint64_t entry) { > + if (GET_TLB_FIELD(entry, PTE_V)) { > + fprintf(f, "0x%016" PRIx64 ": ", entry); > + uint64_t PA =3D hex_tlb_phys_addr(entry); > + uint64_t VA =3D hex_tlb_virt_addr(entry); > + fprintf(f, "V:%" PRId64 " G:%" PRId64 " A1:%" PRId64 " A0:%" = PRId64, > + GET_TLB_FIELD(entry, PTE_V), GET_TLB_FIELD(entry, = PTE_G), > + GET_TLB_FIELD(entry, PTE_ATR1), GET_TLB_FIELD(entry, > PTE_ATR0)); > + fprintf(f, " ASID:0x%02" PRIx64 " VA:0x%08" PRIx64, > + GET_TLB_FIELD(entry, PTE_ASID), VA); > + fprintf(f, > + " X:%" PRId64 " W:%" PRId64 " R:%" PRId64 " U:%" = PRId64 > + " C:%" PRId64, > + GET_TLB_FIELD(entry, PTE_X), GET_TLB_FIELD(entry, = PTE_W), > + GET_TLB_FIELD(entry, PTE_R), GET_TLB_FIELD(entry, = PTE_U), > + GET_TLB_FIELD(entry, PTE_C)); > + fprintf(f, " PA:0x%09" PRIx64 " SZ:%s (0x%" PRIx64 ")", PA, > + pgsize_str[hex_tlb_pgsize_type(entry)], > + hex_tlb_page_size_bytes(entry)); > + fprintf(f, "\n"); > + return true; > + } > + > + /* Not valid */ > + return false; > +} > + > +void dump_mmu(CPUHexagonState *env) > +{ > + int i; > + > + HexagonCPU *cpu =3D env_archcpu(env); > + for (i =3D 0; i < cpu->num_tlbs; i++) { > + uint64_t entry =3D env->hex_tlb->entries[i]; > + if (GET_TLB_FIELD(entry, PTE_V)) { > + qemu_printf("0x%016" PRIx64 ": ", entry); > + uint64_t PA =3D hex_tlb_phys_addr(entry); > + uint64_t VA =3D hex_tlb_virt_addr(entry); > + qemu_printf( > + "V:%" PRId64 " G:%" PRId64 " A1:%" PRId64 " A0:%" = PRId64, > + GET_TLB_FIELD(entry, PTE_V), GET_TLB_FIELD(entry, = PTE_G), > + GET_TLB_FIELD(entry, PTE_ATR1), GET_TLB_FIELD(entry, > PTE_ATR0)); > + qemu_printf(" ASID:0x%02" PRIx64 " VA:0x%08" PRIx64, > + GET_TLB_FIELD(entry, PTE_ASID), VA); > + qemu_printf( > + " X:%" PRId64 " W:%" PRId64 " R:%" PRId64 " U:%" = PRId64 > + " C:%" PRId64, > + GET_TLB_FIELD(entry, PTE_X), GET_TLB_FIELD(entry, = PTE_W), > + GET_TLB_FIELD(entry, PTE_R), GET_TLB_FIELD(entry, = PTE_U), > + GET_TLB_FIELD(entry, PTE_C)); > + qemu_printf(" PA:0x%09" PRIx64 " SZ:%s (0x%" PRIx64 ")", = PA, > + pgsize_str[hex_tlb_pgsize_type(entry)], > + hex_tlb_page_size_bytes(entry)); > + qemu_printf("\n"); Use hex_dump_mmu_entry instead. > + } > + } > +} > + > +static inline void hex_log_tlbw(uint32_t index, uint64_t entry) { > + if (qemu_loglevel_mask(CPU_LOG_MMU)) { > + if (qemu_log_enabled()) { > + FILE *logfile =3D qemu_log_trylock(); > + if (logfile) { > + fprintf(logfile, "tlbw[%03d]: ", index); > + if (!hex_dump_mmu_entry(logfile, entry)) { > + fprintf(logfile, "invalid\n"); > + } > + qemu_log_unlock(logfile); > + } > + } > + } > +} > + > +void hex_tlbw(CPUHexagonState *env, uint32_t index, uint64_t value) { > + uint32_t myidx =3D fTLB_NONPOW2WRAP(fTLB_IDXMASK(index)); > + bool old_entry_valid =3D = GET_TLB_FIELD(env->hex_tlb->entries[myidx], > PTE_V); > + if (old_entry_valid && hexagon_cpu_mmu_enabled(env)) { > + CPUState *cs =3D env_cpu(env); > + > + tlb_flush(cs); > + } > + env->hex_tlb->entries[myidx] =3D (value); > + hex_log_tlbw(myidx, value); > +} > + > +void hex_mmu_realize(CPUHexagonState *env) { > + CPUState *cs =3D env_cpu(env); > + if (cs->cpu_index =3D=3D 0) { > + env->hex_tlb =3D g_malloc0(sizeof(CPUHexagonTLBContext)); > + } else { > + CPUState *cpu0_s =3D NULL; > + CPUHexagonState *env0 =3D NULL; > + CPU_FOREACH(cpu0_s) { > + assert(cpu0_s->cpu_index =3D=3D 0); > + env0 =3D &(HEXAGON_CPU(cpu0_s)->env); > + break; > + } Seems fragile to assume cpu_index =3D=3D 0 will be first in CPU_FOREACH. = This would be better CPU_FOREACH(cpu0_s) { if (cpu0_s->cpu_index =3D=3D 0) { env0 =3D &(HEXAGON_CPU(cpu0_s)->env); break; } } g_assert(env0); /* Make sure we found it */ > + env->hex_tlb =3D env0->hex_tlb; > + } > +} > diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build > index 3ec53010fa..aa729a3683 100644 > --- a/target/hexagon/meson.build > +++ b/target/hexagon/meson.build > @@ -273,7 +273,8 @@ hexagon_ss.add(files( > # idef-generated-enabled-instructions > # > idef_parser_enabled =3D get_option('hexagon_idef_parser') -if > idef_parser_enabled and 'hexagon-linux-user' in target_dirs > +if idef_parser_enabled and ('hexagon-linux-user' in target_dirs or > + 'hexagon-softmmu' in target_dirs) > idef_parser_input_generated =3D custom_target( > 'idef_parser_input.h.inc', > output: 'idef_parser_input.h.inc', Move this to later patch "add build config for softmmu"