From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector
Date: Thu, 14 May 2020 19:54:46 +0200 [thread overview]
Message-ID: <01168f32-c21c-b9fd-cb9c-06511e28bd20@redhat.com> (raw)
In-Reply-To: <44d0486b0fd156a756af544866dd7d19609b1aa6.1588878756.git.alistair.francis@wdc.com>
On 5/7/20 9:13 PM, Alistair Francis wrote:
> If the reset vector is set in the init function don't set it again in
> realise.
typo "realize".
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 20 +++++++++++---------
> 1 file changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 059d71f2c7..8f837edf8d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -111,6 +111,14 @@ static void set_feature(CPURISCVState *env, int feature)
> env->features |= (1ULL << feature);
> }
>
> +static int get_resetvec(CPURISCVState *env)
> +{
> +#ifndef CONFIG_USER_ONLY
> + return env->resetvec;
> +#endif
> + return 0;
Don't you get an error about double return? Maybe use #else?
> +}
> +
> static void set_resetvec(CPURISCVState *env, int resetvec)
> {
> #ifndef CONFIG_USER_ONLY
> @@ -123,7 +131,6 @@ static void riscv_any_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_11_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> }
>
> #if defined(TARGET_RISCV32)
> @@ -140,7 +147,6 @@ static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> set_priv_version(env, PRIV_VERSION_1_09_1);
> - set_resetvec(env, DEFAULT_RSTVEC);
> set_feature(env, RISCV_FEATURE_MMU);
> set_feature(env, RISCV_FEATURE_PMP);
> }
> @@ -150,7 +156,6 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> set_feature(env, RISCV_FEATURE_MMU);
> set_feature(env, RISCV_FEATURE_PMP);
> }
> @@ -160,7 +165,6 @@ static void rv32imacu_nommu_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> set_feature(env, RISCV_FEATURE_PMP);
> }
>
> @@ -169,7 +173,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> set_feature(env, RISCV_FEATURE_PMP);
> }
>
> @@ -187,7 +190,6 @@ static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> set_priv_version(env, PRIV_VERSION_1_09_1);
> - set_resetvec(env, DEFAULT_RSTVEC);
> set_feature(env, RISCV_FEATURE_MMU);
> set_feature(env, RISCV_FEATURE_PMP);
> }
> @@ -197,7 +199,6 @@ static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> set_feature(env, RISCV_FEATURE_MMU);
> set_feature(env, RISCV_FEATURE_PMP);
> }
> @@ -207,7 +208,6 @@ static void rv64imacu_nommu_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> set_feature(env, RISCV_FEATURE_PMP);
> }
>
> @@ -399,7 +399,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> }
>
> set_priv_version(env, priv_version);
> - set_resetvec(env, DEFAULT_RSTVEC);
> + if (!get_resetvec(env)) {
> + set_resetvec(env, DEFAULT_RSTVEC);
> + }
>
> if (cpu->cfg.mmu) {
> set_feature(env, RISCV_FEATURE_MMU);
>
next prev parent reply other threads:[~2020-05-14 17:55 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-07 19:12 [PATCH v2 0/9] RISC-V Add the OpenTitan Machine Alistair Francis
2020-05-07 19:13 ` [PATCH v2 1/9] riscv/boot: Add a missing header include Alistair Francis
2020-05-14 15:33 ` Bin Meng
2020-05-14 15:30 ` Alistair Francis
2020-05-14 15:46 ` Bin Meng
2020-05-14 17:51 ` Philippe Mathieu-Daudé
2020-05-15 5:00 ` Bin Meng
2020-05-07 19:13 ` [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector Alistair Francis
2020-05-14 17:54 ` Philippe Mathieu-Daudé [this message]
2020-05-14 21:42 ` Alistair Francis
2020-05-15 4:54 ` Bin Meng
2020-05-15 19:43 ` Alistair Francis
2020-05-16 9:03 ` Bin Meng
2020-05-19 18:03 ` Alistair Francis
2020-05-07 19:13 ` [PATCH v2 3/9] target/riscv: Add the lowRISC Ibex CPU Alistair Francis
2020-05-15 4:57 ` Bin Meng
2020-05-07 19:13 ` [PATCH v2 4/9] riscv: Initial commit of OpenTitan machine Alistair Francis
2020-05-15 5:14 ` Bin Meng
2020-05-07 19:13 ` [PATCH v2 5/9] hw/char: Initial commit of Ibex UART Alistair Francis
2020-05-14 17:59 ` Philippe Mathieu-Daudé
2020-05-14 21:59 ` Alistair Francis
2020-05-15 7:25 ` Philippe Mathieu-Daudé
2020-05-15 7:28 ` Philippe Mathieu-Daudé
2020-05-15 19:46 ` Alistair Francis
2020-05-07 19:13 ` [PATCH v2 6/9] hw/intc: Initial commit of lowRISC Ibex PLIC Alistair Francis
2020-05-14 18:40 ` Philippe Mathieu-Daudé
2020-05-14 21:53 ` Alistair Francis
2020-05-07 19:13 ` [PATCH v2 7/9] riscv/opentitan: Connect the PLIC device Alistair Francis
2020-05-15 6:29 ` Bin Meng
2020-05-07 19:13 ` [PATCH v2 8/9] riscv/opentitan: Connect the UART device Alistair Francis
2020-05-15 6:29 ` Bin Meng
2020-05-07 19:13 ` [PATCH v2 9/9] target/riscv: Use a smaller guess size for no-MMU PMP Alistair Francis
2020-05-15 6:28 ` Bin Meng
2020-05-13 18:18 ` [PATCH v2 0/9] RISC-V Add the OpenTitan Machine Alistair Francis
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