From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46043) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZXkp4-0007T3-In for qemu-devel@nongnu.org; Fri, 04 Sep 2015 02:50:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZXkp0-0002g9-Id for qemu-devel@nongnu.org; Fri, 04 Sep 2015 02:50:06 -0400 Received: from mailout4.w1.samsung.com ([210.118.77.14]:42758) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZXkp0-0002bB-DH for qemu-devel@nongnu.org; Fri, 04 Sep 2015 02:50:02 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NU500K4W4B97Z20@mailout4.w1.samsung.com> for qemu-devel@nongnu.org; Fri, 04 Sep 2015 07:49:57 +0100 (BST) From: Pavel Fedin Date: Fri, 04 Sep 2015 09:49:56 +0300 Message-id: <012001d0e6dd$e97e8c10$bc7ba430$@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7bit Content-language: ru Subject: [Qemu-devel] PING: [PATCH v2 0/2] cpu_arm: Implement irqchip property for ARM CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: 'Peter Maydell' , 'Shlomo Pongratz' , 'Shlomo Pongratz' Hi! This message is mainly for Peter. I say you reviewed my major sets, but looks like missed this one. If it is OK, we could apply it, and i could successfully bring back the missing part in vGICv3-enabled hw/arm/virt.c which attaches irqchip to CPUs. This would make us more ready for TCG version of GICv3. Kind regards, Pavel Fedin Expert Engineer Samsung Electronics Research center Russia > -----Original Message----- > From: qemu-devel-bounces+p.fedin=samsung.com@nongnu.org [mailto:qemu-devel- > bounces+p.fedin=samsung.com@nongnu.org] On Behalf Of Pavel Fedin > Sent: Tuesday, August 25, 2015 3:18 PM > To: qemu-devel@nongnu.org > Cc: Peter Maydell; Shlomo Pongratz; Shlomo Pongratz > Subject: [Qemu-devel] [PATCH v2 0/2] cpu_arm: Implement irqchip property for ARM CPU > > ARMv7m CPU needs a link to NVIC instance for processing interrupts. > Similarly ARMv8 needs a link to GICv3 for its CPU interface. > > This series builds upon existing mechanism for linking irqchip and > CPU, bringing the code up to date and making it reusable. Another small > step towards complete GICv3 implementation. > > v1 => v2: > - Set link to nvic after it has been initialized > - Changed object type to "sys-bus-device" because GICv2 and GICv3 do not > share common ancestors above that. > > Pavel Fedin (2): > cpu_arm: Rename 'nvic' to 'irqchip' > armv7m: Use irqchip property instead of direct assignment > > hw/arm/armv7m.c | 5 ++--- > target-arm/cpu.c | 6 ++++++ > target-arm/cpu.h | 5 ++++- > target-arm/helper.c | 12 ++++++------ > 4 files changed, 18 insertions(+), 10 deletions(-) > > -- > 1.9.5.msysgit.0