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Wed, 30 Jul 2025 14:21:37 -0700 (PDT) Received: from [192.168.1.87] ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76a167c678esm4696583b3a.5.2025.07.30.14.21.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Jul 2025 14:21:37 -0700 (PDT) Message-ID: <0128c452-8bde-4bdd-b73c-330a7bd619a1@linaro.org> Date: Wed, 30 Jul 2025 14:21:36 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 37/82] target/arm: Convert regime_is_user from switch to table Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org References: <20250727080254.83840-1-richard.henderson@linaro.org> <20250727080254.83840-38-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20250727080254.83840-38-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/27/25 1:02 AM, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > target/arm/internals.h | 17 ----------------- > target/arm/mmuidx-internal.h | 12 ++++++++++++ > target/arm/mmuidx.c | 6 ++++-- > 3 files changed, 16 insertions(+), 19 deletions(-) > > diff --git a/target/arm/internals.h b/target/arm/internals.h > index ea210c7179..c6f3ae470b 100644 > --- a/target/arm/internals.h > +++ b/target/arm/internals.h > @@ -1034,23 +1034,6 @@ static inline bool regime_is_stage2(ARMMMUIdx mmu_idx) > return mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S; > } > > -static inline bool regime_is_user(ARMMMUIdx mmu_idx) > -{ > - switch (mmu_idx) { > - case ARMMMUIdx_E10_0: > - case ARMMMUIdx_E20_0: > - case ARMMMUIdx_E30_0: > - case ARMMMUIdx_Stage1_E0: > - case ARMMMUIdx_MUser: > - case ARMMMUIdx_MSUser: > - case ARMMMUIdx_MUserNegPri: > - case ARMMMUIdx_MSUserNegPri: > - return true; > - default: > - return false; > - } > -} > - > /* Return the SCTLR value which controls this address translation regime */ > static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) > { > diff --git a/target/arm/mmuidx-internal.h b/target/arm/mmuidx-internal.h > index 5a7259a557..ef1f94a23f 100644 > --- a/target/arm/mmuidx-internal.h > +++ b/target/arm/mmuidx-internal.h > @@ -17,6 +17,7 @@ FIELD(MMUIDXINFO, REL, 3, 2) > FIELD(MMUIDXINFO, RELVALID, 5, 1) > FIELD(MMUIDXINFO, 2RANGES, 6, 1) > FIELD(MMUIDXINFO, PAN, 7, 1) > +FIELD(MMUIDXINFO, USER, 8, 1) > > extern const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8]; > > @@ -62,4 +63,15 @@ static inline bool regime_is_pan(ARMMMUIdx idx) > return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, PAN); > } > > +/* > + * Return true if the exception level associated with this mmu index is 0. > + * Differs from arm_mmu_idx_to_el(idx) == 0 in that this allows querying > + * Stage1 and Stage2 mmu indexes. > + */ > +static inline bool regime_is_user(ARMMMUIdx idx) > +{ > + tcg_debug_assert((unsigned)idx < ARRAY_SIZE(arm_mmuidx_table)); > + return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, USER); > +} > + > #endif /* TARGET_ARM_MMUIDX_INTERNAL_H */ > diff --git a/target/arm/mmuidx.c b/target/arm/mmuidx.c > index 98db02b8e5..1c1e062bfe 100644 > --- a/target/arm/mmuidx.c > +++ b/target/arm/mmuidx.c > @@ -7,10 +7,12 @@ > #include "mmuidx-internal.h" > > > -#define EL(X) ((X << R_MMUIDXINFO_EL_SHIFT) | R_MMUIDXINFO_ELVALID_MASK) > +#define EL(X) ((X << R_MMUIDXINFO_EL_SHIFT) | R_MMUIDXINFO_ELVALID_MASK | \ > + ((X == 0) << R_MMUIDXINFO_USER_SHIFT)) > #define REL(X) ((X << R_MMUIDXINFO_REL_SHIFT) | R_MMUIDXINFO_RELVALID_MASK) > #define R2 R_MMUIDXINFO_2RANGES_MASK > #define PAN R_MMUIDXINFO_PAN_MASK > +#define USER R_MMUIDXINFO_USER_MASK > > const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] = { > /* > @@ -33,7 +35,7 @@ const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] = { > [ARMMMUIdx_Stage2_S] = REL(2), > [ARMMMUIdx_Stage2] = REL(2), > > - [ARMMMUIdx_Stage1_E0] = REL(1) | R2, > + [ARMMMUIdx_Stage1_E0] = REL(1) | R2 | USER, > [ARMMMUIdx_Stage1_E1] = REL(1) | R2, > [ARMMMUIdx_Stage1_E1_PAN] = REL(1) | R2 | PAN, > Maybe I missed something, but what about other entries that were initially treated in the switch? - ARMMMUIdx_E.0_0 - ARMMMUIdx_M*User