From: liuzhiwei <zhiwei_liu@c-sky.com>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Alistair Francis <Alistair.Francis@wdc.com>,
qemu-devel@nongnu.org,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
qemu-riscv@nongnu.org
Subject: [Qemu-devel] RISCV: when will the CLIC be ready?
Date: Fri, 16 Aug 2019 11:34:29 +0800 [thread overview]
Message-ID: <0141541d-43ff-98d8-e9d4-4a2fdcfdcf36@c-sky.com> (raw)
Hi, Palmer
When Michael Clark still was the maintainer of RISCV QEMU, he wrote in the mail list, "the CLIC interrupt controller is under testing,
and will be included in QEMU 3.1 or 3.2". It is pity that the CLIC is not in
included even in QEMU 4.1.0.
As we have cpus using CLIC, I have to use the out of tree qemu code in SIFIVE
a long time. Could you tell me when it will be upstreamed?
Best Regards
Zhiwei
next reply other threads:[~2019-08-16 3:40 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-16 3:34 liuzhiwei [this message]
2019-08-16 17:29 ` [Qemu-devel] RISCV: when will the CLIC be ready? Alistair Francis
2019-08-19 13:39 ` liuzhiwei
2019-08-19 16:38 ` [Qemu-devel] [Qemu-riscv] " Chih-Min Chao
2019-08-21 3:33 ` liuzhiwei
2019-08-22 22:38 ` Alistair Francis
2019-08-19 18:56 ` [Qemu-devel] " Alistair Francis
2019-08-20 1:21 ` Bin Meng
2019-08-21 3:01 ` liuzhiwei
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