From: <ltaylorsimpson@gmail.com>
To: "'Brian Cain'" <brian.cain@oss.qualcomm.com>, <qemu-devel@nongnu.org>
Cc: <richard.henderson@linaro.org>, <philmd@linaro.org>,
<quic_mathbern@quicinc.com>, <ale@rev.ng>, <anjo@rev.ng>,
<quic_mliebel@quicinc.com>, <alex.bennee@linaro.org>,
<quic_mburton@quicinc.com>, <sidneym@quicinc.com>,
"'Brian Cain'" <bcain@quicinc.com>
Subject: RE: [PATCH 34/39] target/hexagon: Add TLB, k0 {un,}lock
Date: Tue, 4 Mar 2025 17:09:50 -0600 [thread overview]
Message-ID: <014701db8d5a$8a1ad930$9e508b90$@gmail.com> (raw)
In-Reply-To: <3329ec67-3bf3-425d-b15c-ba77cd8bcd30@oss.qualcomm.com>
> -----Original Message-----
> From: Brian Cain <brian.cain@oss.qualcomm.com>
> Sent: Monday, March 3, 2025 10:24 AM
> To: qemu-devel@nongnu.org
> Cc: richard.henderson@linaro.org; philmd@linaro.org;
> quic_mathbern@quicinc.com; ale@rev.ng; anjo@rev.ng;
> quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com;
> alex.bennee@linaro.org; quic_mburton@quicinc.com;
> sidneym@quicinc.com; Brian Cain <bcain@quicinc.com>
> Subject: Re: [PATCH 34/39] target/hexagon: Add TLB, k0 {un,}lock
>
>
> On 2/28/2025 11:28 PM, Brian Cain wrote:
> > From: Brian Cain <bcain@quicinc.com>
> >
> > Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> > ---
> > target/hexagon/sys_macros.h | 8 +--
> > target/hexagon/op_helper.c | 104
> ++++++++++++++++++++++++++++++++++++
> > 2 files changed, 108 insertions(+), 4 deletions(-)
> >
> > diff --git a/target/hexagon/sys_macros.h b/target/hexagon/sys_macros.h
> > index 3c4c3c7aa5..e5dc1ce0ab 100644
> > --- a/target/hexagon/sys_macros.h
> > +++ b/target/hexagon/sys_macros.h
> > @@ -143,11 +143,11 @@
> > #define fDCINVIDX(REG)
> > #define fDCINVA(REG) do { REG = REG; } while (0) /* Nothing to do in
> > qemu */
> >
> > -#define fSET_TLB_LOCK() g_assert_not_reached()
> > -#define fCLEAR_TLB_LOCK() g_assert_not_reached()
> > +#define fSET_TLB_LOCK() hex_tlb_lock(env);
> > +#define fCLEAR_TLB_LOCK() hex_tlb_unlock(env);
> >
> > -#define fSET_K0_LOCK() g_assert_not_reached()
> > -#define fCLEAR_K0_LOCK() g_assert_not_reached()
> > +#define fSET_K0_LOCK() hex_k0_lock(env);
> > +#define fCLEAR_K0_LOCK() hex_k0_unlock(env);
> >
> > #define fTLB_IDXMASK(INDEX) \
> > ((INDEX) & (fPOW2_ROUNDUP(fCAST4u(env_archcpu(env)-
> >num_tlbs)) -
> > 1)) diff --git a/target/hexagon/op_helper.c
> > b/target/hexagon/op_helper.c index 702c3dd3c6..f3b14fbf58 100644
> > --- a/target/hexagon/op_helper.c
> > +++ b/target/hexagon/op_helper.c
> > @@ -1184,6 +1184,110 @@ void HELPER(modify_ssr)(CPUHexagonState
> *env, uint32_t new, uint32_t old)
> > BQL_LOCK_GUARD();
> > hexagon_modify_ssr(env, new, old);
> > }
> > +
> > +static void hex_k0_lock(CPUHexagonState *env) {
> > + BQL_LOCK_GUARD();
> > + g_assert((env->k0_lock_count == 0) || (env->k0_lock_count == 1));
> > +
> > + uint32_t syscfg = arch_get_system_reg(env, HEX_SREG_SYSCFG);
Minor nit - registers should be target_ulong type.
> > + if (GET_SYSCFG_FIELD(SYSCFG_K0LOCK, syscfg)) {
> > + if (env->k0_lock_state == HEX_LOCK_QUEUED) {
Are HEX_LOCK_* defined in an earlier patch in this series. Can we move the definitions here?
> > + env->next_PC += 4;
> > + env->k0_lock_count++;
> > + env->k0_lock_state = HEX_LOCK_OWNER;
> > + SET_SYSCFG_FIELD(env, SYSCFG_K0LOCK, 1);
> > + return;
> > + }
> > + if (env->k0_lock_state == HEX_LOCK_OWNER) {
> > + qemu_log_mask(LOG_GUEST_ERROR,
> > + "Double k0lock at PC: 0x%x, thread may hang\n",
> > + env->next_PC);
> > + env->next_PC += 4;
> > + CPUState *cs = env_cpu(env);
> > + cpu_interrupt(cs, CPU_INTERRUPT_HALT);
> > + return;
> > + }
> > + env->k0_lock_state = HEX_LOCK_WAITING;
> > + CPUState *cs = env_cpu(env);
> > + cpu_interrupt(cs, CPU_INTERRUPT_HALT);
> > + } else {
> > + env->next_PC += 4;
> > + env->k0_lock_count++;
> > + env->k0_lock_state = HEX_LOCK_OWNER;
> > + SET_SYSCFG_FIELD(env, SYSCFG_K0LOCK, 1);
> > + }
> > +
> > +}
>
> This was discussed previously at
> https://lore.kernel.org/qemu-
> devel/CH3PR02MB102479550F96F09E0C9D50BA7B87B2@CH3PR02MB10247.n
> amprd02.prod.outlook.com/
>
> We have taken some but not all of the suggestions from then. One of our
> concerns is regarding an architectural requirement for "fairness" with regards
> to picking the hardware thread to be selected to pass the lock to. If we
> unleash the thundering herd, does this just mean that the fairness is
> dependent on the host scheduler design / configuration?
>
> Also - I note that we didn't take the suggestions regarding cpu_loop_exit /
> cpu_loop_exit_restore. That was an oversight, the next revision will include
> that update.
>
> > +
> > +static void hex_k0_unlock(CPUHexagonState *env) {
> > + BQL_LOCK_GUARD();
> > + g_assert((env->k0_lock_count == 0) || (env->k0_lock_count == 1));
> > +
> > + /* Nothing to do if the k0 isn't locked by this thread */
> > + uint32_t syscfg = arch_get_system_reg(env, HEX_SREG_SYSCFG);
target_ulong
> > + if ((GET_SYSCFG_FIELD(SYSCFG_K0LOCK, syscfg) == 0) ||
> > + (env->k0_lock_state != HEX_LOCK_OWNER)) {
> > + qemu_log_mask(LOG_GUEST_ERROR,
> > + "thread %d attempted to unlock k0 without having the "
> > + "lock, k0_lock state = %d, syscfg:k0 = %d\n",
> > + env->threadId, env->k0_lock_state,
> > + GET_SYSCFG_FIELD(SYSCFG_K0LOCK, syscfg));
> > + g_assert(env->k0_lock_state != HEX_LOCK_WAITING);
> > + return;
> > + }
> > +
> > + env->k0_lock_count--;
> > + env->k0_lock_state = HEX_LOCK_UNLOCKED;
> > + SET_SYSCFG_FIELD(env, SYSCFG_K0LOCK, 0);
> > +
> > + /* Look for a thread to unlock */
> > + unsigned int this_threadId = env->threadId;
> > + CPUHexagonState *unlock_thread = NULL;
> > + CPUState *cs;
> > + CPU_FOREACH(cs) {
> > + CPUHexagonState *thread = cpu_env(cs);
> > +
> > + /*
> > + * The hardware implements round-robin fairness, so we look for
> threads
> > + * starting at env->threadId + 1 and incrementing modulo the number
> of
> > + * threads.
> > + *
> > + * To implement this, we check if thread is a earlier in the modulo
> > + * sequence than unlock_thread.
> > + * if unlock thread is higher than this thread
> > + * thread must be between this thread and unlock_thread
> > + * else
> > + * thread higher than this thread is ahead of unlock_thread
> > + * thread must be lower then unlock thread
> > + */
> > + if (thread->k0_lock_state == HEX_LOCK_WAITING) {
> > + if (!unlock_thread) {
> > + unlock_thread = thread;
> > + } else if (unlock_thread->threadId > this_threadId) {
> > + if (this_threadId < thread->threadId &&
> > + thread->threadId < unlock_thread->threadId) {
> > + unlock_thread = thread;
> > + }
> > + } else {
> > + if (thread->threadId > this_threadId) {
> > + unlock_thread = thread;
> > + }
> > + if (thread->threadId < unlock_thread->threadId) {
> > + unlock_thread = thread;
> > + }
> > + }
> > + }
> > + }
> > + if (unlock_thread) {
> > + cs = env_cpu(unlock_thread);
> > + unlock_thread->k0_lock_state = HEX_LOCK_QUEUED;
> > + SET_SYSCFG_FIELD(unlock_thread, SYSCFG_K0LOCK, 1);
> > + cpu_interrupt(cs, CPU_INTERRUPT_K0_UNLOCK);
> > + }
> > +
> > +}
> > #endif
> >
> >
next prev parent reply other threads:[~2025-03-04 23:10 UTC|newest]
Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-01 5:28 [PATCH 00/39] hexagon system emu, part 2/3 Brian Cain
2025-03-01 5:28 ` [PATCH 01/39] target/hexagon: Implement ciad helper Brian Cain
2025-03-17 16:08 ` ltaylorsimpson
2025-03-18 14:44 ` Sid Manning
2025-09-02 1:32 ` Brian Cain
2025-03-01 5:28 ` [PATCH 02/39] target/hexagon: Implement {c,}swi helpers Brian Cain
2025-03-17 16:09 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 03/39] target/hexagon: Implement iassign{r,w} helpers Brian Cain
2025-03-17 16:20 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 04/39] target/hexagon: Implement start/stop helpers Brian Cain
2025-03-17 16:35 ` ltaylorsimpson
2025-09-02 1:33 ` Brian Cain
2025-03-01 5:28 ` [PATCH 05/39] target/hexagon: Implement modify SSR Brian Cain
2025-03-17 17:37 ` ltaylorsimpson
2025-03-18 18:34 ` Sid Manning
2025-03-18 19:14 ` ltaylorsimpson
2025-03-18 23:47 ` Brian Cain
2025-03-19 16:39 ` ltaylorsimpson
2025-03-19 16:58 ` Richard Henderson
2025-09-02 1:39 ` Brian Cain
2025-03-01 5:28 ` [PATCH 06/39] target/hexagon: Implement {g,s}etimask helpers Brian Cain
2025-03-17 17:44 ` ltaylorsimpson
2025-03-21 21:48 ` Sid Manning
2025-09-02 1:44 ` Brian Cain
2025-03-01 5:28 ` [PATCH 07/39] target/hexagon: Implement wait helper Brian Cain
2025-03-17 18:37 ` ltaylorsimpson
2025-09-02 1:46 ` Brian Cain
2025-03-01 5:28 ` [PATCH 08/39] target/hexagon: Implement get_exe_mode() Brian Cain
2025-03-17 18:43 ` ltaylorsimpson
2025-04-02 2:03 ` Brian Cain
2025-03-01 5:28 ` [PATCH 09/39] target/hexagon: Implement arch_get_system_reg() Brian Cain
2025-03-17 18:46 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 10/39] target/hexagon: Implement arch_{s, g}et_{thread, system}_reg() Brian Cain via
2025-03-17 19:24 ` ltaylorsimpson
2025-09-02 1:50 ` [PATCH 10/39] target/hexagon: Implement arch_{s,g}et_{thread,system}_reg() Brian Cain
2025-03-01 5:28 ` [PATCH 11/39] target/hexagon: Add representation to count cycles Brian Cain
2025-03-17 19:33 ` ltaylorsimpson
2025-09-02 1:52 ` Brian Cain
2025-03-01 5:28 ` [PATCH 12/39] target/hexagon: Add implementation of cycle counters Brian Cain
2025-03-19 19:50 ` ltaylorsimpson
2025-04-02 2:44 ` Brian Cain
[not found] ` <7274cd69-f4e7-40b5-b850-cbd9099ed8ac@oss.qualcomm.com>
2025-09-02 1:56 ` Brian Cain
2025-03-01 5:28 ` [PATCH 13/39] target/hexagon: Implement modify_syscfg() Brian Cain
2025-03-19 21:12 ` ltaylorsimpson
2025-09-02 1:58 ` Brian Cain
2025-03-01 5:28 ` [PATCH 14/39] target/hexagon: Add system event, cause codes Brian Cain
2025-03-17 19:40 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 15/39] target/hexagon: Implement hex_tlb_entry_get_perm() Brian Cain
2025-03-17 19:37 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 16/39] target/hexagon: Implement hex_tlb_lookup_by_asid() Brian Cain
2025-03-17 19:42 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 17/39] target/hexagon: Implement software interrupt Brian Cain
2025-03-19 21:28 ` ltaylorsimpson
2025-03-24 15:51 ` Sid Manning
2025-09-02 2:03 ` Brian Cain
2025-03-01 5:28 ` [PATCH 18/39] target/hexagon: Implement exec_interrupt, set_irq Brian Cain
2025-03-19 21:33 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 19/39] target/hexagon: Implement hexagon_tlb_fill() Brian Cain
2025-03-17 19:55 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 20/39] target/hexagon: Implement siad inst Brian Cain
2025-03-17 19:57 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 21/39] target/hexagon: Implement hexagon_resume_threads() Brian Cain
2025-03-19 21:36 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 22/39] target/hexagon: Implement setprio, resched Brian Cain
2025-03-20 19:44 ` ltaylorsimpson
2025-03-20 20:25 ` Sid Manning
2025-03-20 22:28 ` ltaylorsimpson
2025-09-02 2:08 ` Brian Cain
2025-03-01 5:28 ` [PATCH 23/39] target/hexagon: Add sysemu_ops, cpu_get_phys_page_debug() Brian Cain
2025-03-20 20:02 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 24/39] target/hexagon: Add exec-start-addr prop Brian Cain
2025-03-17 20:03 ` ltaylorsimpson
2025-09-02 2:12 ` Brian Cain
2025-03-01 5:28 ` [PATCH 25/39] target/hexagon: Add hexagon_cpu_mmu_index() Brian Cain
2025-03-17 20:07 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 26/39] target/hexagon: Decode trap1, rte as COF Brian Cain
2025-03-17 20:08 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 27/39] target/hexagon: Implement hexagon_find_last_irq() Brian Cain
2025-03-17 20:09 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 28/39] target/hexagon: Implement modify_ssr, resched, pending_interrupt Brian Cain
2025-03-17 20:12 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 29/39] target/hexagon: Add pkt_ends_tb to translation Brian Cain
2025-03-17 20:20 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 30/39] target/hexagon: Add next_PC, {s,g}reg writes Brian Cain
2025-03-18 18:50 ` ltaylorsimpson
2025-09-02 2:35 ` Brian Cain
2025-03-01 5:28 ` [PATCH 31/39] target/hexagon: Add implicit sysreg writes Brian Cain
2025-03-18 19:18 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 32/39] target/hexagon: Define system, guest reg names Brian Cain
2025-03-19 16:48 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 33/39] target/hexagon: initialize sys/guest reg TCGvs Brian Cain
2025-03-19 16:53 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 34/39] target/hexagon: Add TLB, k0 {un,}lock Brian Cain
2025-03-03 16:24 ` Brian Cain
2025-03-04 23:09 ` ltaylorsimpson [this message]
2025-03-04 23:57 ` Philippe Mathieu-Daudé
2025-03-05 0:05 ` ltaylorsimpson
2025-03-05 0:19 ` Philippe Mathieu-Daudé
2025-03-05 0:45 ` ltaylorsimpson
2025-03-19 17:01 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 35/39] target/hexagon: Define gen_precise_exception() Brian Cain
2025-03-19 17:20 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 36/39] target/hexagon: Add TCG overrides for transfer insts Brian Cain
2025-03-19 17:22 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 37/39] target/hexagon: Add support for loadw_phys Brian Cain
2025-03-20 20:04 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 38/39] target/hexagon: Add guest reg reading functionality Brian Cain
2025-03-19 18:36 ` ltaylorsimpson
2025-09-02 2:40 ` Brian Cain
2025-03-01 5:28 ` [PATCH 39/39] target/hexagon: Add pcycle setting functionality Brian Cain
2025-03-19 18:49 ` ltaylorsimpson
2025-09-02 2:42 ` Brian Cain
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