From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com
Subject: Re: [PATCH v4 02/10] target/riscv: remove RISCV_FEATURE_MISA
Date: Thu, 16 Feb 2023 12:26:29 -0300 [thread overview]
Message-ID: <014d3ae9-58a1-9ee1-0aea-df4a81a9a032@ventanamicro.com> (raw)
In-Reply-To: <20230216145212.dvgb5isazcx52w6i@orel>
On 2/16/23 11:52, Andrew Jones wrote:
> On Thu, Feb 16, 2023 at 10:04:36AM -0300, Daniel Henrique Barboza wrote:
>> It's unused after write_misa() became a regular no-op.
>>
>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> ---
>> target/riscv/cpu.h | 1 -
>> 1 file changed, 1 deletion(-)
>>
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 7128438d8e..01803a020d 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -89,7 +89,6 @@ enum {
>> RISCV_FEATURE_MMU,
>> RISCV_FEATURE_PMP,
>> RISCV_FEATURE_EPMP,
>> - RISCV_FEATURE_MISA,
>> RISCV_FEATURE_DEBUG
>> };
>>
>> --
>> 2.39.1
>>
>
> Probably could squash into the previous patch, but anyway
True. Since we have a typo to fix in there I'll squash this in.
Thanks,
Daniel
>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>
> Thanks,
> drew
next prev parent reply other threads:[~2023-02-16 15:27 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-16 13:04 [PATCH v4 00/10] make write_misa a no-op and FEATURE_* cleanups Daniel Henrique Barboza
2023-02-16 13:04 ` [PATCH v4 01/10] target/riscv: turn write_misa() into an official no-op Daniel Henrique Barboza
2023-02-16 13:26 ` Bin Meng
2023-02-16 14:51 ` Andrew Jones
2023-02-16 13:04 ` [PATCH v4 02/10] target/riscv: remove RISCV_FEATURE_MISA Daniel Henrique Barboza
2023-02-16 13:31 ` Bin Meng
2023-02-16 14:52 ` Andrew Jones
2023-02-16 15:26 ` Daniel Henrique Barboza [this message]
2023-02-16 13:04 ` [PATCH v4 03/10] target/riscv: introduce riscv_cpu_cfg() Daniel Henrique Barboza
2023-02-16 13:04 ` [PATCH v4 04/10] target/riscv: remove RISCV_FEATURE_DEBUG Daniel Henrique Barboza
2023-02-16 13:04 ` [PATCH v4 05/10] target/riscv/cpu.c: error out if EPMP is enabled without PMP Daniel Henrique Barboza
2023-02-16 13:04 ` [PATCH v4 06/10] target/riscv: remove RISCV_FEATURE_EPMP Daniel Henrique Barboza
2023-02-16 13:04 ` [PATCH v4 07/10] target/riscv: remove RISCV_FEATURE_PMP Daniel Henrique Barboza
2023-02-16 13:04 ` [PATCH v4 08/10] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus() Daniel Henrique Barboza
2023-02-16 13:04 ` [PATCH v4 09/10] target/riscv: remove RISCV_FEATURE_MMU Daniel Henrique Barboza
2023-02-16 13:04 ` [PATCH v4 10/10] target/riscv/cpu: remove CPUArchState::features and friends Daniel Henrique Barboza
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=014d3ae9-58a1-9ee1-0aea-df4a81a9a032@ventanamicro.com \
--to=dbarboza@ventanamicro.com \
--cc=ajones@ventanamicro.com \
--cc=alistair.francis@wdc.com \
--cc=bmeng@tinylab.org \
--cc=liweiwei@iscas.ac.cn \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).