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Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v9 08/14] hw/nvram: NPCM7xx OTP device model To: "Avi.Fishman@nuvoton.com" , Havard Skinnemoen , "peter.maydell@linaro.org" Cc: "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "KFTING@nuvoton.com" , Alexander Bulekov , Shengtan Mao , Hao Wu , Chris Rauer References: <20200911052101.2602693-1-hskinnemoen@google.com> <20200911052101.2602693-9-hskinnemoen@google.com> <6ccd925d-b965-4da0-13f2-365bd75abe88@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/3/23 08:41, Avi.Fishman@nuvoton.com wrote: > Hi, > > Inside > > >> -----Original Message----- >> From: Philippe Mathieu-Daudé >> Sent: Thursday, December 22, 2022 5:03 PM >> To: Havard Skinnemoen ; peter.maydell@linaro.org >> Cc: qemu-arm@nongnu.org; qemu-devel@nongnu.org; IS20 Avi Fishman >> ; CS20 KFTing ; Alexander >> Bulekov ; Shengtan Mao ; Hao Wu >> ; Chris Rauer ; CS20 KFTing >> >> Subject: Re: [PATCH v9 08/14] hw/nvram: NPCM7xx OTP device model >> >> Hi, >> >> (old patch) >> >> On 11/9/20 07:20, Havard Skinnemoen wrote: >>> This supports reading and writing OTP fuses and keys. Only fuse reading >>> has been tested. Protection is not implemented. >>> >>> Reviewed-by: Avi Fishman >>> Reviewed-by: Philippe Mathieu-Daudé >>> Tested-by: Philippe Mathieu-Daudé >>> Tested-by: Alexander Bulekov >>> Signed-off-by: Havard Skinnemoen >>> --- >>> include/hw/arm/npcm7xx.h | 3 + >>> include/hw/nvram/npcm7xx_otp.h | 79 ++++++ >>> hw/arm/npcm7xx.c | 29 +++ >>> hw/nvram/npcm7xx_otp.c | 440 +++++++++++++++++++++++++++++++++ >>> hw/nvram/meson.build | 1 + >>> 5 files changed, 552 insertions(+) >>> create mode 100644 include/hw/nvram/npcm7xx_otp.h >>> create mode 100644 hw/nvram/npcm7xx_otp.c >> >>> +/** >>> + * npcm7xx_otp_array_write - ECC encode and write data to OTP array. >>> + * @s: OTP module. >>> + * @data: Data to be encoded and written. >>> + * @offset: Offset of first byte to be written in the OTP array. >>> + * @len: Number of bytes before ECC encoding. >>> + * >>> + * Each nibble of data is encoded into a byte, so the number of bytes written >>> + * to the array will be @len * 2. >>> + */ >>> +extern void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void >> *data, >>> + unsigned int offset, unsigned int len); >> >>> +static void npcm7xx_init_fuses(NPCM7xxState *s) >>> +{ >>> + NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); >>> + uint32_t value; >>> + >>> + /* >>> + * The initial mask of disabled modules indicates the chip derivative (e.g. >>> + * NPCM750 or NPCM730). >>> + */ >>> + value = tswap32(nc->disabled_modules); >> >> In which endianness do you want this 32-bit fuse value to be written? > > It should be little endian, I am not sure why there is a swap here. > Unless the nc->disabled_modules for some reason is coming swapped so we swap it back. > >> >> I suppose you used a little-endian host, so we want it big-endian in >> the OTP? In that case it would be better to use cpu_to_be32(), to >> be able to use the OTP on a big-endian host such s390x. > > So according to what I said then use cpu_to_le32() Thank you Avi!