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[176.170.216.159]) by smtp.gmail.com with ESMTPSA id 10-20020a170906218a00b009c0c511bd62sm6722714eju.197.2023.10.23.08.03.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Oct 2023 08:03:55 -0700 (PDT) Message-ID: <0177b29e-ee73-d266-3ce0-6541bc2db649@linaro.org> Date: Mon, 23 Oct 2023 17:03:52 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v6 07/10] hw/arm: Hook up FSI module in AST2600 Content-Language: en-US To: Ninad Palsule , qemu-devel@nongnu.org, clg@kaod.org, peter.maydell@linaro.org, andrew@codeconstruct.com.au, joel@jms.id.au, pbonzini@redhat.com, marcandre.lureau@redhat.com, berrange@redhat.com, thuth@redhat.com, lvivier@redhat.com Cc: qemu-arm@nongnu.org, Andrew Jeffery References: <20231021211720.3571082-1-ninad@linux.ibm.com> <20231021211720.3571082-8-ninad@linux.ibm.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20231021211720.3571082-8-ninad@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=philmd@linaro.org; helo=mail-ej1-x62a.google.com X-Spam_score_int: -53 X-Spam_score: -5.4 X-Spam_bar: ----- X-Spam_report: (-5.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-3.339, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 21/10/23 23:17, Ninad Palsule wrote: > This patchset introduces IBM's Flexible Service Interface(FSI). > > Time for some fun with inter-processor buses. FSI allows a service > processor access to the internal buses of a host POWER processor to > perform configuration or debugging. > > FSI has long existed in POWER processes and so comes with some baggage, > including how it has been integrated into the ASPEED SoC. > > Working backwards from the POWER processor, the fundamental pieces of > interest for the implementation are: > > 1. The Common FRU Access Macro (CFAM), an address space containing > various "engines" that drive accesses on buses internal and external > to the POWER chip. Examples include the SBEFIFO and I2C masters. The > engines hang off of an internal Local Bus (LBUS) which is described > by the CFAM configuration block. > > 2. The FSI slave: The slave is the terminal point of the FSI bus for > FSI symbols addressed to it. Slaves can be cascaded off of one > another. The slave's configuration registers appear in address space > of the CFAM to which it is attached. > > 3. The FSI master: A controller in the platform service processor (e.g. > BMC) driving CFAM engine accesses into the POWER chip. At the > hardware level FSI is a bit-based protocol supporting synchronous and > DMA-driven accesses of engines in a CFAM. > > 4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in > POWER processors. This now makes an appearance in the ASPEED SoC due > to tight integration of the FSI master IP with the OPB, mainly the > existence of an MMIO-mapping of the CFAM address straight onto a > sub-region of the OPB address space. > > 5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in > the AST2600. Hardware limitations prevent the OPB from being directly > mapped into APB, so all accesses are indirect through the bridge. > > The implementation appears as following in the qemu device tree: > > (qemu) info qtree > bus: main-system-bus > type System > ... > dev: aspeed.apb2opb, id "" > gpio-out "sysbus-irq" 1 > mmio 000000001e79b000/0000000000001000 > bus: opb.1 > type opb > dev: fsi.master, id "" > bus: fsi.bus.1 > type fsi.bus > dev: cfam.config, id "" > dev: cfam, id "" > bus: fsi.lbus.1 > type lbus > dev: scratchpad, id "" > address = 0 (0x0) > bus: opb.0 > type opb > dev: fsi.master, id "" > bus: fsi.bus.0 > type fsi.bus > dev: cfam.config, id "" > dev: cfam, id "" > bus: fsi.lbus.0 > type lbus > dev: scratchpad, id "" > address = 0 (0x0) > > The LBUS is modelled to maintain the qdev bus hierarchy and to take > advantage of the object model to automatically generate the CFAM > configuration block. The configuration block presents engines in the > order they are attached to the CFAM's LBUS. Engine implementations > should subclass the LBusDevice and set the 'config' member of > LBusDeviceClass to match the engine's type. > > CFAM designs offer a lot of flexibility, for instance it is possible for > a CFAM to be simultaneously driven from multiple FSI links. The modeling > is not so complete; it's assumed that each CFAM is attached to a single > FSI slave (as a consequence the CFAM subclasses the FSI slave). > > As for FSI, its symbols and wire-protocol are not modelled at all. This > is not necessary to get FSI off the ground thanks to the mapping of the > CFAM address space onto the OPB address space - the models follow this > directly and map the CFAM memory region into the OPB's memory region. > Future work includes supporting more advanced accesses that drive the > FSI master directly rather than indirectly via the CFAM mapping, which > will require implementing the FSI state machine and methods for each of > the FSI symbols on the slave. Further down the track we can also look at > supporting the bitbanged SoftFSI drivers in Linux by extending the FSI > slave model to resolve sequences of GPIO IRQs into FSI symbols, and > calling the associated symbol method on the slave to map the access onto > the CFAM. > > Testing: > Tested by reading cfam config address 0 on rainier machine type. > > root@p10bmc:~# pdbg -a getcfam 0x0 > p0: 0x0 = 0xc0022d15 > > Signed-off-by: Andrew Jeffery > Signed-off-by: Ninad Palsule > --- > include/hw/arm/aspeed_soc.h | 4 ++++ > hw/arm/aspeed_ast2600.c | 19 +++++++++++++++++++ > 2 files changed, 23 insertions(+) Reviewed-by: Philippe Mathieu-Daudé