RE: [PATCH 11/39] target/hexagon: Add representation to count cycles

[<ltaylorsimpson@gmail.com>]

> -----Original Message-----
> From: Brian Cain <brian.cain@oss.qualcomm.com>
> Sent: Friday, February 28, 2025 11:28 PM
> To: qemu-devel@nongnu.org
> Cc: brian.cain@oss.qualcomm.com; richard.henderson@linaro.org;
> philmd@linaro.org; quic_mathbern@quicinc.com; ale@rev.ng; anjo@rev.ng;
> quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com;
> alex.bennee@linaro.org; quic_mburton@quicinc.com;
> sidneym@quicinc.com; Brian Cain <bcain@quicinc.com>
> Subject: [PATCH 11/39] target/hexagon: Add representation to count cycles
> 
> From: Brian Cain <bcain@quicinc.com>
> 
> The PCYCLE register can be enabled to indicate accumulated clock cycles.
> 
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> ---
>  target/hexagon/cpu.h     |  3 ++-
>  target/hexagon/cpu.c     |  3 +++
>  target/hexagon/machine.c | 25 ++++++++++++++++++++++++-
>  3 files changed, 29 insertions(+), 2 deletions(-)
> 
> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index
> 1549c4f1f0..4b9c9873dc 100644
> --- a/target/hexagon/cpu.h
> +++ b/target/hexagon/cpu.h
> @@ -113,7 +113,8 @@ typedef struct CPUArchState {
>      target_ulong stack_start;
> 
>      uint8_t slot_cancelled;
> -
> +    uint64_t t_cycle_count;
> +    uint64_t *g_pcycle_base;
>  #ifndef CONFIG_USER_ONLY
>      /* Some system registers are per thread and some are global. */
>      target_ulong t_sreg[NUM_SREGS];
> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index
> 84a96a194b..89a051b41d 100644
> --- a/target/hexagon/cpu.c
> +++ b/target/hexagon/cpu.c
> @@ -335,6 +335,7 @@ static void hexagon_cpu_reset_hold(Object *obj,
> ResetType type)
> 
>      if (cs->cpu_index == 0) {
>          arch_set_system_reg(env, HEX_SREG_MODECTL, 0x1);
> +        *(env->g_pcycle_base) = 0;

See discussion on shared resources.

>      }
>      mmu_reset(env);
>      arch_set_system_reg(env, HEX_SREG_HTID, cs->cpu_index); @@ -396,10
> +397,12 @@ static void hexagon_cpu_realize(DeviceState *dev, Error
> **errp)  #ifndef CONFIG_USER_ONLY
>      if (cs->cpu_index == 0) {
>          env->g_sreg = g_new0(target_ulong, NUM_SREGS);
> +        env->g_pcycle_base = g_malloc0(sizeof(*env->g_pcycle_base));

Shared resource ...

>      } else {
>          CPUState *cpu0 = qemu_get_cpu(0);
>          CPUHexagonState *env0 = cpu_env(cpu0);
>          env->g_sreg = env0->g_sreg;
> +        env->g_pcycle_base = env0->g_pcycle_base;

Shared resource ...