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From: Pavel Fedin <p.fedin@samsung.com>
To: 'Eric Auger' <eric.auger@linaro.org>,
	'Peter Maydell' <peter.maydell@linaro.org>
Cc: 'QEMU Developers' <qemu-devel@nongnu.org>,
	'Christoffer Dall' <christoffer.dall@linaro.org>,
	kvmarm@lists.cs.columbia.edu
Subject: Re: [Qemu-devel] [PATCH v3 4/4] target-arm: Add the GICv2m to the	virt board
Date: Tue, 26 May 2015 16:54:17 +0300	[thread overview]
Message-ID: <019801d097bb$75764c70$6062e550$@samsung.com> (raw)
In-Reply-To: <5564702F.2030308@linaro.org>

 Hi! My word...

> What is your guidance, should we introduce new memory maps for GICv3
> enabled machine or should we move to a single dynamic memory map?

 IMHO there's no reason to introduce another memory map. I have already done test integration some time ago, and here is what i got:
--- cut ---
enum {
    VIRT_FLASH,
    VIRT_MEM,
    VIRT_CPUPERIPHS,
    VIRT_GIC_DIST,
    VIRT_GIC_CPU,
    VIRT_GIC_DIST_SPI = VIRT_GIC_CPU,
    VIRT_ITS_CONTROL,
    VIRT_ITS_TRANSLATION,
    VIRT_LPI,
    VIRT_UART,
    VIRT_MMIO,
    VIRT_RTC,
    VIRT_FW_CFG,
    VIRT_PCIE,
    VIRT_GIC_V2M = VIRT_ITS_CONTROL,
};
--- cut ---
static const MemMapEntry a15memmap[] = {
    /* Space up to 0x8000000 is reserved for a boot ROM */
    [VIRT_FLASH] =           {          0, 0x08000000 },
    [VIRT_CPUPERIPHS] =      { 0x08000000, 0x00020000 },
    /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
    [VIRT_GIC_DIST] =        { 0x08000000, 0x00010000 },
    [VIRT_GIC_CPU] =         { 0x08010000, 0x00010000 }, /* VIRT_GIC_DIST_SPI for v3 */
    [VIRT_ITS_CONTROL] =     { 0x08020000, 0x0010000 }, /* VIRT_GIC_V2M for v2 */
    [VIRT_ITS_TRANSLATION] = { 0x08030000, 0x00010000 },
    [VIRT_LPI] =             { 0x08040000, 0x00800000 },
    [VIRT_UART] =            { 0x09000000, 0x00001000 },
    [VIRT_RTC] =             { 0x09010000, 0x00001000 },
    [VIRT_FW_CFG] =          { 0x09020000, 0x0000000a },
    [VIRT_MMIO] =            { 0x0a000000, 0x00000200 },
    /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
    /*
     * PCIE verbose map:
     *
     * MMIO window      { 0x10000000, 0x2eff0000 },
     * PIO window       { 0x3eff0000, 0x00010000 },
     * ECAM             { 0x3f000000, 0x01000000 },
     */
    [VIRT_PCIE] =       { 0x10000000, 0x30000000 },
    [VIRT_MEM] =        { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
};
--- cut ---
 As you can see, it's perfectly readable and memory maps are identical. I even see no problem with merging ITS_CONTROL and ITS_TRANSPATION, because i don't see any harm in increasing v2m area.
 P.S. And yes, VIRT_GIC_DIST_SPI should be VIRT_GIC_DIST_MBI instead (Reviewed-by: Eric Auger <eric.auger@linaro.org>), just this fragment is from my old integration branch, which i currently don't work on, because my new test environment doesn't use GICv2 at all.

Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia

      parent reply	other threads:[~2015-05-26 13:54 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-24 10:51 [Qemu-devel] [PATCH v3 0/4] Add support for for GICv2m and MSIs to arm-virt Christoffer Dall
2015-05-24 10:51 ` [Qemu-devel] [PATCH v3 1/4] target-arm: Add GIC phandle to VirtBoardInfo Christoffer Dall
2015-05-26 12:24   ` Eric Auger
2015-05-24 10:51 ` [Qemu-devel] [PATCH v3 2/4] arm_gicv2m: Add GICv2m widget to support MSIs Christoffer Dall
2015-05-26 12:24   ` Eric Auger
2015-05-24 10:51 ` [Qemu-devel] [PATCH v3 3/4] target-arm: Extend the gic node properties Christoffer Dall
2015-05-26 12:54   ` Eric Auger
2015-05-24 10:51 ` [Qemu-devel] [PATCH v3 4/4] target-arm: Add the GICv2m to the virt board Christoffer Dall
2015-05-25 13:09   ` Pavel Fedin
2015-05-25 15:01     ` Peter Maydell
2015-05-25 16:25       ` Eric Auger
2015-05-26  6:39         ` Pavel Fedin
2015-05-25 20:56     ` Christoffer Dall
2015-05-26 12:54   ` Eric Auger
2015-05-26 12:55     ` Peter Maydell
2015-05-26 13:07       ` Eric Auger
2015-05-26 13:52         ` Peter Maydell
2015-05-26 13:54         ` Pavel Fedin [this message]

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