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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736c16c72ddsm8785162b3a.177.2025.03.12.07.32.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Mar 2025 07:32:47 -0700 (PDT) Message-ID: <01af330a-d5c0-4d0e-bda2-0a3908dacd6e@linaro.org> Date: Wed, 12 Mar 2025 07:32:45 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/1] util/cacheflush: Make first DSB unconditional on aarch64 To: Peter Maydell , Joe Komlodi Cc: qemu-devel@nongnu.org, slongfield@google.com, pbonzini@redhat.com References: <20250310203622.1827940-1-komlodi@google.com> <20250310203622.1827940-2-komlodi@google.com> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/12/25 07:18, Peter Maydell wrote: > On Mon, 10 Mar 2025 at 20:36, Joe Komlodi wrote: >> >> On ARM hosts with CTR_EL0.DIC and CTR_EL0.IDC set, this would only cause >> an ISB to be executed during cache maintenance, which could lead to QEMU >> executing TBs containing garbage instructions. >> >> This seems to be because the ISB finishes executing instructions and >> flushes the pipeline, but the ISB doesn't guarantee that writes from the >> executed instructions are committed. If a small enough TB is created, it's >> possible that the writes setting up the TB aren't committed by the time the >> TB is executed. > > Yes; we need the DSB to ensure that the stores have completed > and are visible to subsequent icache fills; and then we need > the ISB to ensure that any instructions that we execute after > this are done with an instruction fetch that happens after the > ISB (i.e. the CPU hasn't already speculatively fetched the insn > before we forced the store to complete). > >> This function is intended to be a port of the gcc implementation >> (https://github.com/gcc-mirror/gcc/blob/85b46d0795ac76bc192cb8f88b646a647acf98c1/libgcc/config/aarch64/sync-cache.c#L67) >> which makes the first DSB unconditional, so we can fix the synchronization >> issue by doing that as well. >> >> Signed-off-by: Joe Komlodi Reviewed-by: Richard Henderson > Richard, are you doing a TCG pullreq for rc0? If not, I can > put this into target-arm.next. So far I have nothing queued for tcg. Please go ahead. r~