[PULL 0/3] aspeed queue

[PULL 0/3] aspeed queue

[Cédric Le Goater]

The following changes since commit afc9fcde55296b83f659de9da3cdf044812a6eeb:

  Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2021-10-20 06:10:51 -0700)

are available in the Git repository at:

  https://github.com/legoater/qemu/ tags/pull-aspeed-20211022

for you to fetch changes up to b12fa6118f4d838d19720ec6476a1666a1b43474:

  speed/sdhci: Add trace events (2021-10-22 09:52:17 +0200)

----------------------------------------------------------------
Aspeed patches :

* New fp5280g2-bmc board (John)
* Small cleanup in Aspeed SMC model (Cedric)

----------------------------------------------------------------
Cédric Le Goater (2):
      aspeed/smc: Use a container for the flash mmio address space
      speed/sdhci: Add trace events

John Wang (1):
      aspeed: Add support for the fp5280g2-bmc board

 include/hw/ssi/aspeed_smc.h |  2 +-
 hw/arm/aspeed.c             | 74 +++++++++++++++++++++++++++++++++++++++++++++
 hw/sd/aspeed_sdhci.c        |  5 +++
 hw/ssi/aspeed_smc.c         | 11 ++++---
 hw/sd/trace-events          |  4 +++
 5 files changed, 91 insertions(+), 5 deletions(-)

[PULL 1/3] aspeed: Add support for the fp5280g2-bmc board

[Cédric Le Goater]

From: John Wang <wangzq.jn@gmail.com>

The fp5280g2-bmc is supported by OpenBMC, It's
based on the following device tree

https://github.com/openbmc/linux/blob/dev-5.10/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts

Signed-off-by: John Wang <wangzhiqiang02@inspur.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211014064548.934799-1-wangzhiqiang02@inspur.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index f5916e81262e..a77f46b3adba 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -131,6 +131,21 @@ struct AspeedMachineState {
         SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) |                       \
         SCU_AST2500_HW_STRAP_RESERVED1)
 
+/* FP5280G2 hardware value: 0XF100D286 */
+#define FP5280G2_BMC_HW_STRAP1 (                                      \
+        SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
+        SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
+        SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
+        SCU_AST2500_HW_STRAP_RESERVED28 |                               \
+        SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
+        SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
+        SCU_HW_STRAP_LPC_RESET_PIN |                                    \
+        SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
+        SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
+        SCU_HW_STRAP_MAC1_RGMII |                                       \
+        SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
+        SCU_AST2500_HW_STRAP_RESERVED1)
+
 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
 
@@ -430,6 +445,15 @@ static void aspeed_machine_init(MachineState *machine)
     arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
 }
 
+static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
+{
+    I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
+    DeviceState *dev = DEVICE(i2c_dev);
+
+    qdev_prop_set_uint32(dev, "rom-size", rsize);
+    i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
+}
+
 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
 {
     AspeedSoCState *soc = &bmc->soc;
@@ -689,6 +713,34 @@ static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
     i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
 }
 
+static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
+{
+    AspeedSoCState *soc = &bmc->soc;
+    I2CSlave *i2c_mux;
+
+    /* The at24c256 */
+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
+
+    /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
+                     0x48);
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
+                     0x49);
+
+    i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
+                     "pca9546", 0x70);
+    /* It expects a TMP112 but a TMP105 is compatible */
+    i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
+                     0x4a);
+
+    /* It expects a ds3232 but a ds1338 is good enough */
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
+
+    /* It expects a pca9555 but a pca9552 is compatible */
+    i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_PCA9552,
+                     0x20);
+}
+
 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
 {
     AspeedSoCState *soc = &bmc->soc;
@@ -1140,6 +1192,24 @@ static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
         aspeed_soc_num_cpus(amc->soc_name);
 };
 
+static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+    mc->desc       = "Inspur FP5280G2 BMC (ARM1176)";
+    amc->soc_name  = "ast2500-a1";
+    amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
+    amc->fmc_model = "n25q512a";
+    amc->spi_model = "mx25l25635e";
+    amc->num_cs    = 2;
+    amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
+    amc->i2c_init  = fp5280g2_bmc_i2c_init;
+    mc->default_ram_size = 512 * MiB;
+    mc->default_cpus = mc->min_cpus = mc->max_cpus =
+        aspeed_soc_num_cpus(amc->soc_name);
+};
+
 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
@@ -1227,6 +1297,10 @@ static const TypeInfo aspeed_machine_types[] = {
         .name          = MACHINE_TYPE_NAME("g220a-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_g220a_class_init,
+    }, {
+        .name          = MACHINE_TYPE_NAME("fp5280g2-bmc"),
+        .parent        = TYPE_ASPEED_MACHINE,
+        .class_init    = aspeed_machine_fp5280g2_class_init,
     }, {
         .name          = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
-- 
2.31.1

[PULL 2/3] aspeed/smc: Use a container for the flash mmio address space

[Cédric Le Goater]

Because AddressSpaces must not be sysbus-mapped, commit e9c568dbc225
("hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use
alias") introduced an alias for the flash mmio region.

Using a container is cleaner.

Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20211018132609.160008-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/ssi/aspeed_smc.h |  2 +-
 hw/ssi/aspeed_smc.c         | 11 +++++++----
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
index 75bc793bd269..e26555581996 100644
--- a/include/hw/ssi/aspeed_smc.h
+++ b/include/hw/ssi/aspeed_smc.h
@@ -52,8 +52,8 @@ struct AspeedSMCState {
     SysBusDevice parent_obj;
 
     MemoryRegion mmio;
+    MemoryRegion mmio_flash_container;
     MemoryRegion mmio_flash;
-    MemoryRegion mmio_flash_alias;
 
     qemu_irq irq;
 
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 8a988c167604..ff154eb84f85 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -1151,14 +1151,17 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
      * window in which the flash modules are mapped. The size and
      * address depends on the SoC model and controller type.
      */
+    memory_region_init(&s->mmio_flash_container, OBJECT(s),
+                       TYPE_ASPEED_SMC ".container",
+                       asc->flash_window_size);
+    sysbus_init_mmio(sbd, &s->mmio_flash_container);
+
     memory_region_init_io(&s->mmio_flash, OBJECT(s),
                           &aspeed_smc_flash_default_ops, s,
                           TYPE_ASPEED_SMC ".flash",
                           asc->flash_window_size);
-    memory_region_init_alias(&s->mmio_flash_alias, OBJECT(s),
-                             TYPE_ASPEED_SMC ".flash",
-                             &s->mmio_flash, 0, asc->flash_window_size);
-    sysbus_init_mmio(sbd, &s->mmio_flash_alias);
+    memory_region_add_subregion(&s->mmio_flash_container, 0x0,
+                                &s->mmio_flash);
 
     /*
      * Let's create a sub memory region for each possible peripheral. All
-- 
2.31.1

[PULL 3/3] speed/sdhci: Add trace events

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20211018132609.160008-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/sd/aspeed_sdhci.c | 5 +++++
 hw/sd/trace-events   | 4 ++++
 2 files changed, 9 insertions(+)

diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
index 3299844de6dc..df1bdf1fa4ed 100644
--- a/hw/sd/aspeed_sdhci.c
+++ b/hw/sd/aspeed_sdhci.c
@@ -14,6 +14,7 @@
 #include "hw/irq.h"
 #include "migration/vmstate.h"
 #include "hw/qdev-properties.h"
+#include "trace.h"
 
 #define ASPEED_SDHCI_INFO            0x00
 #define  ASPEED_SDHCI_INFO_SLOT1     (1 << 17)
@@ -60,6 +61,8 @@ static uint64_t aspeed_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
         }
     }
 
+    trace_aspeed_sdhci_read(addr, size, (uint64_t) val);
+
     return (uint64_t)val;
 }
 
@@ -68,6 +71,8 @@ static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
 {
     AspeedSDHCIState *sdhci = opaque;
 
+    trace_aspeed_sdhci_write(addr, size, val);
+
     switch (addr) {
     case ASPEED_SDHCI_INFO:
         /* The RESET bit automatically clears. */
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
index 3cc2ef89ba6b..94a00557b26f 100644
--- a/hw/sd/trace-events
+++ b/hw/sd/trace-events
@@ -68,3 +68,7 @@ pl181_fifo_push(uint32_t data) "FIFO push 0x%08" PRIx32
 pl181_fifo_pop(uint32_t data) "FIFO pop 0x%08" PRIx32
 pl181_fifo_transfer_complete(void) "FIFO transfer complete"
 pl181_data_engine_idle(void) "data engine idle"
+
+# aspeed_sdhci.c
+aspeed_sdhci_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
+aspeed_sdhci_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
-- 
2.31.1

Re: [PULL 0/3] aspeed queue

[Richard Henderson]

On 10/22/21 12:57 AM, Cédric Le Goater wrote:
> The following changes since commit afc9fcde55296b83f659de9da3cdf044812a6eeb:
> 
>    Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2021-10-20 06:10:51 -0700)
> 
> are available in the Git repository at:
> 
>    https://github.com/legoater/qemu/ tags/pull-aspeed-20211022
> 
> for you to fetch changes up to b12fa6118f4d838d19720ec6476a1666a1b43474:
> 
>    speed/sdhci: Add trace events (2021-10-22 09:52:17 +0200)
> 
> ----------------------------------------------------------------
> Aspeed patches :
> 
> * New fp5280g2-bmc board (John)
> * Small cleanup in Aspeed SMC model (Cedric)
> 
> ----------------------------------------------------------------
> Cédric Le Goater (2):
>        aspeed/smc: Use a container for the flash mmio address space
>        speed/sdhci: Add trace events
> 
> John Wang (1):
>        aspeed: Add support for the fp5280g2-bmc board
> 
>   include/hw/ssi/aspeed_smc.h |  2 +-
>   hw/arm/aspeed.c             | 74 +++++++++++++++++++++++++++++++++++++++++++++
>   hw/sd/aspeed_sdhci.c        |  5 +++
>   hw/ssi/aspeed_smc.c         | 11 ++++---
>   hw/sd/trace-events          |  4 +++
>   5 files changed, 91 insertions(+), 5 deletions(-)

Applied, thanks.

r~

[PULL 0/3] aspeed queue

[Cédric Le Goater]

The following changes since commit 527dede083d3e3e5a13ee996776926e0a0c4e258:

  Merge tag 'pull-request-2025-03-19' of https://gitlab.com/thuth/qemu into staging (2025-03-20 08:41:25 -0400)

are available in the Git repository at:

  https://github.com/legoater/qemu/ tags/pull-aspeed-20250323

for you to fetch changes up to 78877b2e06464f49f777e086845e094ea7bc82ef:

  hw/misc/aspeed_hace: Fix buffer overflow in has_padding function (2025-03-23 18:42:16 +0100)

----------------------------------------------------------------
aspeed queue:

* Fix AST2700 SoC model

----------------------------------------------------------------
Jamin Lin (1):
      hw/misc/aspeed_hace: Fix buffer overflow in has_padding function

Steven Lee (1):
      hw/intc/aspeed: Fix IRQ handler mask check

Troy Lee (1):
      aspeed: Fix maximum number of spi controller

 include/hw/arm/aspeed_soc.h | 2 +-
 hw/intc/aspeed_intc.c       | 2 +-
 hw/misc/aspeed_hace.c       | 5 +++++
 3 files changed, 7 insertions(+), 2 deletions(-)

Re: [PULL 0/3] aspeed queue

[Stefan Hajnoczi]

[-- Attachment #1: Type: text/plain, Size: 116 bytes --]

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

Re: [PULL 0/3] aspeed queue

[Michael Tokarev]

23.03.2025 20:45, Cédric Le Goater wrote:
> Jamin Lin (1):
>        hw/misc/aspeed_hace: Fix buffer overflow in has_padding function
> 
> Steven Lee (1):
>        hw/intc/aspeed: Fix IRQ handler mask check
> 
> Troy Lee (1):
>        aspeed: Fix maximum number of spi controller

Is there anything in there worth to pick up for stable series?

Thanks,

/mjt

Re: [PULL 0/3] aspeed queue

[Cédric Le Goater]

On 3/24/25 21:36, Michael Tokarev wrote:
> 23.03.2025 20:45, Cédric Le Goater wrote:
>> Jamin Lin (1):
>>        hw/misc/aspeed_hace: Fix buffer overflow in has_padding function
>>
>> Steven Lee (1):
>>        hw/intc/aspeed: Fix IRQ handler mask check
>>
>> Troy Lee (1):
>>        aspeed: Fix maximum number of spi controller
> 
> Is there anything in there worth to pick up for stable series?


you are fast !

- "aspeed: Fix maximum number of spi controller" is QEMU 10.0 material.
- "hw/intc/aspeed: Fix IRQ handler mask check" was merged in QEMU 9.1
- "hw/misc/aspeed_hace: Fix buffer overflow in has_padding function"
    was merged in QEMU 7.1

The last 2 deserve to be backported IMO. They will need some massaging.


Thanks,

C.

Re: [PULL 0/3] aspeed queue

[Michael Tokarev]

24.03.2025 23:46, Cédric Le Goater wrote:

>> Is there anything in there worth to pick up for stable series?
> 
> you are fast !

I was just about to send final announcements for a bunch of next
stable releases, and noticed another pull request has been merged.. :)


> - "aspeed: Fix maximum number of spi controller" is QEMU 10.0 material.
> - "hw/intc/aspeed: Fix IRQ handler mask check" was merged in QEMU 9.1
> - "hw/misc/aspeed_hace: Fix buffer overflow in has_padding function"
>     was merged in QEMU 7.1
> 
> The last 2 deserve to be backported IMO. They will need some massaging.

The "buffer overflow" fix seems to be okay for 9.2, 8.2 and 7.2.

The "IRQ handler mask check" seems to be this (for 9.2). Does it look sane?

Author: Steven Lee <steven_lee@aspeedtech.com>
Date:   Thu Mar 20 17:25:43 2025 +0800

     hw/intc/aspeed: Fix IRQ handler mask check

     Updated the IRQ handler mask check to AND with select variable.
     This ensures that the interrupt service routine is correctly triggered
     for the interrupts within the same irq group.

     For example, both `eth0` and the debug UART are handled in `GICINT132`.
     Without this fix, the debug console may hang if the `eth0` ISR is not
     handled.

     Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
     Change-Id: Ic3609eb72218dfd68be6057d78b8953b18828709
     Reviewed-by: Cédric Le Goater <clg@redhat.com>
     Fixes: d831c5fd8682 ("aspeed/intc: Add AST2700 support")
     Link: https://lore.kernel.org/qemu-devel/20250320092543.4040672-2-steven_lee@aspeedtech.com
     Signed-off-by: Cédric Le Goater <clg@redhat.com>
     (cherry picked from commit 7b8cbe5162e69ad629c5326bf3c158b81857955d)
     (Mjt: update for before v9.2.0-2466-g5824e8bf6beb
      "hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication")
     Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>

diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 126b711b94..495fd2bdfa 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -92,7 +92,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)

      trace_aspeed_intc_select(select);

-    if (s->mask[irq] || s->regs[status_addr]) {
+    if ((s->mask[irq] & select) || (s->regs[status_addr] & select)) {
          /*
           * a. mask is not 0 means in ISR mode
           * sources interrupt routine are executing.

Re: [PULL 0/3] aspeed queue

[Cédric Le Goater]

On 3/24/25 22:08, Michael Tokarev wrote:
> 24.03.2025 23:46, Cédric Le Goater wrote:
> 
>>> Is there anything in there worth to pick up for stable series?
>>
>> you are fast !
> 
> I was just about to send final announcements for a bunch of next
> stable releases, and noticed another pull request has been merged.. :)
> 
> 
>> - "aspeed: Fix maximum number of spi controller" is QEMU 10.0 material.
>> - "hw/intc/aspeed: Fix IRQ handler mask check" was merged in QEMU 9.1
>> - "hw/misc/aspeed_hace: Fix buffer overflow in has_padding function"
>>     was merged in QEMU 7.1
>>
>> The last 2 deserve to be backported IMO. They will need some massaging.
> 
> The "buffer overflow" fix seems to be okay for 9.2, 8.2 and 7.2.
> 
> The "IRQ handler mask check" seems to be this (for 9.2). Does it look sane?

It does.

Thanks,

C.




> Author: Steven Lee <steven_lee@aspeedtech.com>
> Date:   Thu Mar 20 17:25:43 2025 +0800
> 
>      hw/intc/aspeed: Fix IRQ handler mask check
> 
>      Updated the IRQ handler mask check to AND with select variable.
>      This ensures that the interrupt service routine is correctly triggered
>      for the interrupts within the same irq group.
> 
>      For example, both `eth0` and the debug UART are handled in `GICINT132`.
>      Without this fix, the debug console may hang if the `eth0` ISR is not
>      handled.
> 
>      Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
>      Change-Id: Ic3609eb72218dfd68be6057d78b8953b18828709
>      Reviewed-by: Cédric Le Goater <clg@redhat.com>
>      Fixes: d831c5fd8682 ("aspeed/intc: Add AST2700 support")
>      Link: https://lore.kernel.org/qemu-devel/20250320092543.4040672-2-steven_lee@aspeedtech.com
>      Signed-off-by: Cédric Le Goater <clg@redhat.com>
>      (cherry picked from commit 7b8cbe5162e69ad629c5326bf3c158b81857955d)
>      (Mjt: update for before v9.2.0-2466-g5824e8bf6beb
>       "hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication")
>      Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
> 
> diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
> index 126b711b94..495fd2bdfa 100644
> --- a/hw/intc/aspeed_intc.c
> +++ b/hw/intc/aspeed_intc.c
> @@ -92,7 +92,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)
> 
>       trace_aspeed_intc_select(select);
> 
> -    if (s->mask[irq] || s->regs[status_addr]) {
> +    if ((s->mask[irq] & select) || (s->regs[status_addr] & select)) {
>           /*
>            * a. mask is not 0 means in ISR mode
>            * sources interrupt routine are executing.
> 

[PULL 0/3] aspeed queue

[Cédric Le Goater]

The following changes since commit de39a045bd8d2b49e4f3d07976622c29d58e0bac:

  Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200915-pull-request' into staging (2020-09-15 14:25:05 +0100)

are available in the Git repository at:

  https://github.com/legoater/qemu/ tags/pull-aspeed-20200918

for you to fetch changes up to 204dab83fe00a3e0781d93ad7899192a9409e987:

  misc: aspeed_scu: Update AST2600 silicon id register (2020-09-18 09:04:36 +0200)

----------------------------------------------------------------
Aspeed patches :

* Couple of cleanups
* New machine properties to define the flash models

----------------------------------------------------------------
Cédric Le Goater (1):
      hw/arm/aspeed: Add machine properties to define the flash models

Joel Stanley (1):
      misc: aspeed_scu: Update AST2600 silicon id register

Philippe Mathieu-Daudé (1):
      hw/arm/aspeed: Map the UART5 device unconditionally

 docs/system/arm/aspeed.rst | 18 ++++++++++++++++++
 hw/arm/aspeed.c            | 45 +++++++++++++++++++++++++++++++++++++++++++--
 hw/arm/aspeed_ast2600.c    |  8 +++-----
 hw/arm/aspeed_soc.c        |  8 +++-----
 hw/misc/aspeed_scu.c       |  7 ++++++-
 5 files changed, 73 insertions(+), 13 deletions(-)

Re: [PULL 0/3] aspeed queue

[no-reply]

Patchew URL: https://patchew.org/QEMU/20200918072703.331138-1-clg@kaod.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

N/A. Internal error while reading log file



The full log is available at
http://patchew.org/logs/20200918072703.331138-1-clg@kaod.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

Re: [PULL 0/3] aspeed queue

[Peter Maydell]

On Fri, 18 Sep 2020 at 08:27, Cédric Le Goater <clg@kaod.org> wrote:
>
> The following changes since commit de39a045bd8d2b49e4f3d07976622c29d58e0bac:
>
>   Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200915-pull-request' into staging (2020-09-15 14:25:05 +0100)
>
> are available in the Git repository at:
>
>   https://github.com/legoater/qemu/ tags/pull-aspeed-20200918
>
> for you to fetch changes up to 204dab83fe00a3e0781d93ad7899192a9409e987:
>
>   misc: aspeed_scu: Update AST2600 silicon id register (2020-09-18 09:04:36 +0200)
>
> ----------------------------------------------------------------
> Aspeed patches :
>
> * Couple of cleanups
> * New machine properties to define the flash models
>
> ----------------------------------------------------------------


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2
for any user-visible changes.

-- PMM