From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>, qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
Aleksandar Rikalo <arikalo@gmail.com>
Subject: Re: [PATCH v3 1/9] target/mips: Extract decode_64bit_enabled() helper
Date: Wed, 30 Oct 2024 15:46:31 -0700 [thread overview]
Message-ID: <01f61fd9-d46d-48bd-bc2c-4b3cb78ac17c@linaro.org> (raw)
In-Reply-To: <20241026175349.84523-2-philmd@linaro.org>
On 10/26/24 10:53, Philippe Mathieu-Daudé wrote:
> Extract the decode_64bit_enabled() helper which detects
> whether CPUs can run 64-bit instructions.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/mips/tcg/translate.h | 2 ++
> target/mips/tcg/translate.c | 7 ++++++-
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
> index 5d196e69ac4..ae6c25aa0c4 100644
> --- a/target/mips/tcg/translate.h
> +++ b/target/mips/tcg/translate.h
> @@ -217,6 +217,8 @@ void msa_translate_init(void);
> void mxu_translate_init(void);
> bool decode_ase_mxu(DisasContext *ctx, uint32_t insn);
>
> +bool decode_64bit_enabled(DisasContext *ctx);
> +
> /* decodetree generated */
> bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
> bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
> diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
> index d92fc418edd..6c881af5618 100644
> --- a/target/mips/tcg/translate.c
> +++ b/target/mips/tcg/translate.c
> @@ -1645,13 +1645,18 @@ static inline void check_ps(DisasContext *ctx)
> check_cp1_64bitmode(ctx);
> }
>
> +bool decode_64bit_enabled(DisasContext *ctx)
> +{
> + return ctx->hflags & MIPS_HFLAG_64;
> +}
> +
> /*
> * This code generates a "reserved instruction" exception if cpu is not
> * 64-bit or 64-bit instructions are not enabled.
> */
> void check_mips_64(DisasContext *ctx)
> {
> - if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) {
> + if (unlikely((TARGET_LONG_BITS != 64) || !decode_64bit_enabled(ctx))) {
> gen_reserved_instruction(ctx);
> }
> }
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
next prev parent reply other threads:[~2024-10-30 22:47 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-26 17:53 [PATCH v3 0/9] target/mips: Convert Loongson LEXT opcodes to decodetree Philippe Mathieu-Daudé
2024-10-26 17:53 ` [PATCH v3 1/9] target/mips: Extract decode_64bit_enabled() helper Philippe Mathieu-Daudé
2024-10-30 22:46 ` Pierrick Bouvier [this message]
2024-10-26 17:53 ` [PATCH v3 2/9] target/mips: Simplify Loongson MULTU.G opcode Philippe Mathieu-Daudé
2024-10-26 17:53 ` [PATCH v3 3/9] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP Philippe Mathieu-Daudé
2024-10-26 17:53 ` [PATCH v3 4/9] target/mips: Convert Loongson DDIV.G opcodes to decodetree Philippe Mathieu-Daudé
2024-10-26 17:53 ` [PATCH v3 5/9] target/mips: Convert Loongson DIV.G " Philippe Mathieu-Daudé
2024-10-26 17:53 ` [PATCH v3 6/9] target/mips: Convert Loongson [D]DIVU.G " Philippe Mathieu-Daudé
2024-10-26 17:53 ` [PATCH v3 7/9] target/mips: Convert Loongson [D]MOD[U].G " Philippe Mathieu-Daudé
2024-10-26 17:53 ` [PATCH v3 8/9] target/mips: Convert Loongson [D]MULT[U].G " Philippe Mathieu-Daudé
2024-10-26 17:53 ` [PATCH v3 9/9] target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext Philippe Mathieu-Daudé
2024-10-30 22:47 ` Pierrick Bouvier
2024-10-26 17:55 ` [PATCH v3 0/9] target/mips: Convert Loongson LEXT opcodes to decodetree Philippe Mathieu-Daudé
2024-10-31 3:54 ` Philippe Mathieu-Daudé
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