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From: "Philippe Mathieu-Daudé" <philippe.mathieu.daude@gmail.com>
To: Alistair Francis <alistair.francis@opensource.wdc.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: wilfred.mallawa@wdc.com, alistair.francis@wdc.com,
	bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com
Subject: Re: [PATCH v2 2/2] riscv: opentitan: Connect opentitan SPI Host
Date: Tue, 1 Mar 2022 00:44:15 +0100	[thread overview]
Message-ID: <0215dda2-9b9f-f0cf-32a9-3c64340aab79@gmail.com> (raw)
In-Reply-To: <20220228034047.34612-2-alistair.francis@opensource.wdc.com>

On 28/2/22 04:40, Alistair Francis wrote:
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> 
> Conenct spi host[1/0] to opentitan.

Typo "Connect".

> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> ---
>   hw/riscv/opentitan.c         | 36 ++++++++++++++++++++++++++++++++----
>   include/hw/riscv/opentitan.h | 12 +++++++++++-
>   2 files changed, 43 insertions(+), 5 deletions(-)
> 
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 833624d66c..2d401dcb23 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -120,11 +120,18 @@ static void lowrisc_ibex_soc_init(Object *obj)
>       object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
>   
>       object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
> +
> +    for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) {
> +        object_initialize_child(obj, "spi_host[*]", &s->spi_host[i],
> +                                TYPE_IBEX_SPI_HOST);
> +    }
>   }
>   
>   static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
>   {
>       const MemMapEntry *memmap = ibex_memmap;
> +    DeviceState *dev;
> +    SysBusDevice *busdev;
>       MachineState *ms = MACHINE(qdev_get_machine());
>       LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
>       MemoryRegion *sys_mem = get_system_memory();
> @@ -209,14 +216,35 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
>                             qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)),
>                                              IRQ_M_TIMER));
>   
> +    /* SPI-Hosts */
> +    for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) {
> +        dev = DEVICE(&(s->spi_host[i]));
> +        if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi_host[i]), errp)) {

FYI if this fails for i=1, spi_host[0] is not deallocated. Not sure how
to improve this.

> +            return;
> +        }
> +        busdev = SYS_BUS_DEVICE(dev);
> +        sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base);

> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index 00da9ded43..3a3f412ef8 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -1,7 +1,7 @@

> +#define OPENTITAN_NUM_SPI_HOSTS 2
> +#define OPENTITAN_SPI_HOST0 0
> +#define OPENTITAN_SPI_HOST1 1

Eventuallt enum.

>   enum {
>       IBEX_TIMER_TIMEREXPIRED0_0 = 126,
> +    IBEX_SPI_HOST1_SPI_EVENT_IRQ = 153,
> +    IBEX_SPI_HOST1_ERR_IRQ = 152,
> +    IBEX_SPI_HOST0_SPI_EVENT_IRQ = 151,
> +    IBEX_SPI_HOST0_ERR_IRQ = 150,
>       IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
>       IBEX_UART0_RX_TIMEOUT_IRQ = 7,
>       IBEX_UART0_RX_BREAK_ERR_IRQ = 6,

It would be nice to get this enum somehow sorted.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  parent reply	other threads:[~2022-03-01  0:18 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-28  3:40 [PATCH v2 1/2] hw/ssi: Add Ibex SPI device model Alistair Francis
2022-02-28  3:40 ` [PATCH v2 2/2] riscv: opentitan: Connect opentitan SPI Host Alistair Francis
2022-02-28  8:31   ` Alistair Francis
2022-02-28 23:44   ` Philippe Mathieu-Daudé [this message]
2022-02-28  9:13 ` [PATCH v2 1/2] hw/ssi: Add Ibex SPI device model Alistair Francis
2022-02-28 23:52   ` Philippe Mathieu-Daudé

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