From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, bmeng.cn@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v4 1/5] target/riscv: Add a virtualised MMU Mode
Date: Wed, 4 Nov 2020 08:24:24 -0800 [thread overview]
Message-ID: <021fc366-fcdb-3646-5fc4-0ff5790e6b34@linaro.org> (raw)
In-Reply-To: <4b301bc0ea36da962fc1605371b65019ac3073df.1604464950.git.alistair.francis@wdc.com>
On 11/3/20 8:43 PM, Alistair Francis wrote:
> -#define NB_MMU_MODES 4
> +/*
> + * The current MMU Modes are:
> + * - U mode 0b000
> + * - S mode 0b001
> + * - M mode 0b011
> + * - U mode HLV/HLVX/HSV 0b100
> + * - S mode HLV/HLVX/HSV 0b101
> + * - M mode HLV/HLVX/HSV 0b111
> + */
> +#define NB_MMU_MODES 6
6 modes, but you're leaving two holes, so you need 8 here.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2020-11-04 16:26 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-04 4:43 [PATCH v4 0/5] Fix the Hypervisor access functions Alistair Francis
2020-11-04 4:43 ` [PATCH v4 1/5] target/riscv: Add a virtualised MMU Mode Alistair Francis
2020-11-04 16:24 ` Richard Henderson [this message]
2020-11-04 4:43 ` [PATCH v4 2/5] target/riscv: Set the virtualised MMU mode when doing hyp accesses Alistair Francis
2020-11-04 4:43 ` [PATCH v4 3/5] target/riscv: Remove the HS_TWO_STAGE flag Alistair Francis
2020-11-04 4:43 ` [PATCH v4 4/5] target/riscv: Remove the hyp load and store functions Alistair Francis
2020-11-04 16:30 ` Richard Henderson
2020-11-04 4:43 ` [PATCH v4 5/5] target/riscv: Split the Hypervisor execute load helpers Alistair Francis
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