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([2001:b07:6468:f312:5e2c:eb9a:a8b6:fd3e]) by smtp.googlemail.com with ESMTPSA id w2-20020adfd4c2000000b00225307f43fbsm1625940wrk.44.2022.11.11.03.08.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Nov 2022 03:08:40 -0800 (PST) Message-ID: <022fd97e-3500-5830-9a22-7caadc03d5a0@redhat.com> Date: Fri, 11 Nov 2022 12:08:39 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Subject: Re: should ioapic_service really be modelling cpu writes? Content-Language: en-US To: Peter Xu , =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: QEMU Developers , "Michael S. Tsirkin" , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Peter Maydell References: <874jv6enct.fsf@linaro.org> <87zgcyd70g.fsf@linaro.org> From: Paolo Bonzini In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/10/22 23:42, Peter Xu wrote: > I think it shouldn't? Normally the irq will be in MSI format (IOAPIC will > translate to an MSI in QEMU, per ioapic_entry_parse()). > > I had a feeling that it'll just go the shortcut here (MSI always starts > with 0xfeeXXXXX so definitely bigger than 0xfff): Note that QEMU subtracts 0xfee00000 by the time you get to apic_mem_write, but still yes, that's what happens for IOAPIC. The write is on the PCI bus. > if (addr > 0xfff || !index) { > /* MSI and MMIO APIC are at the same memory location, > * but actually not on the global bus: MSI is on PCI bus > * APIC is connected directly to the CPU. > * Mapping them on the global bus happens to work because > * MSI registers are reserved in APIC MMIO and vice versa. */ > MSIMessage msi = { .address = addr, .data = val }; > apic_send_msi(&msi); > return; > } > > apic_send_msi() doesn't need a cpu context. Alex, perhaps you can change the shortcut to if (size < 4) { return; } dev = cpu_get_current_apic(memtxattrs); if (!dev) { /* comment here... */ MSIMessage msi = { .address = addr, .data = val }; apic_send_msi(&msi); return; } s = APIC(dev); ... Paolo