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From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: Nicholas Piggin <npiggin@gmail.com>, qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Subject: Re: [PATCH v1 1/2] target/ppc: PMU do not clear MMCR0[FCECE] on performance monitor alert
Date: Mon, 5 Jun 2023 08:10:26 -0300	[thread overview]
Message-ID: <0237ea14-67c9-b4bf-e656-8337487df427@gmail.com> (raw)
In-Reply-To: <20230530134313.387252-1-npiggin@gmail.com>



On 5/30/23 10:43, Nicholas Piggin wrote:
> FCECE does not get cleared according to the ISA v3.1B.
> 
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>

And queued.


Daniel

>   target/ppc/power8-pmu.c | 1 -
>   1 file changed, 1 deletion(-)
> 
> diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
> index c4c331c6b5..af065115f2 100644
> --- a/target/ppc/power8-pmu.c
> +++ b/target/ppc/power8-pmu.c
> @@ -289,7 +289,6 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu)
>       pmu_update_cycles(env);
>   
>       if (env->spr[SPR_POWER_MMCR0] & MMCR0_FCECE) {
> -        env->spr[SPR_POWER_MMCR0] &= ~MMCR0_FCECE;
>           env->spr[SPR_POWER_MMCR0] |= MMCR0_FC;
>   
>           /* Changing MMCR0_FC requires summaries and hflags update */


      parent reply	other threads:[~2023-06-05 11:11 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-30 13:43 [PATCH v1 1/2] target/ppc: PMU do not clear MMCR0[FCECE] on performance monitor alert Nicholas Piggin
2023-05-30 13:43 ` [PATCH v1 2/2] target/ppc: PMU implement PERFM interrupts Nicholas Piggin
2023-06-05 11:10   ` Daniel Henrique Barboza
2023-06-05 11:10 ` Daniel Henrique Barboza [this message]

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