From: <ltaylorsimpson@gmail.com>
To: "'Matheus Tavares Bernardino'" <quic_mathbern@quicinc.com>,
<qemu-devel@nongnu.org>
Cc: <sidneym@quicinc.com>, <bcain@quicinc.com>,
<richard.henderson@linaro.org>, <ale@rev.ng>, <anjo@rev.ng>
Subject: RE: [PATCH] Hexagon: fix HVX store new
Date: Mon, 20 May 2024 14:57:54 -0500 [thread overview]
Message-ID: <029b01daaaf0$01eaf7e0$05c0e7a0$@gmail.com> (raw)
In-Reply-To: <f548dc1c240819c724245e887f29f918441e9125.1716220379.git.quic_mathbern@quicinc.com>
> -----Original Message-----
> From: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
> Sent: Monday, May 20, 2024 10:53 AM
> To: qemu-devel@nongnu.org
> Cc: ltaylorsimpson@gmail.com; sidneym@quicinc.com; bcain@quicinc.com;
> richard.henderson@linaro.org; ale@rev.ng; anjo@rev.ng
> Subject: [PATCH] Hexagon: fix HVX store new
>
> At 09a7e7db0f (Hexagon (target/hexagon) Remove uses of
> op_regs_generated.h.inc, 2024-03-06), we've changed the logic of
> check_new_value() to use the new pre-calculated
> packet->insn[...].dest_idx instead of calculating the index on the fly
> using opcode_reginfo[...]. The dest_idx index is calculated roughly like
the
> following:
>
> for reg in iset[tag]["syntax"]:
> if reg.is_written():
> dest_idx = regno
> break
>
> Thus, we take the first register that is writtable. Before that, however,
we
> also used to follow an alphabetical order on the register
> type: 'd', 'e', 'x', and 'y'. No longer following that makes us select the
wrong
> register index and the HVX store new instruction does not update the
> memory like expected.
>
> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
next prev parent reply other threads:[~2024-05-20 19:58 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-20 15:53 [PATCH] Hexagon: fix HVX store new Matheus Tavares Bernardino
2024-05-20 16:21 ` Brian Cain
2024-05-20 19:57 ` ltaylorsimpson [this message]
2024-06-06 3:16 ` Brian Cain
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