From: <ltaylorsimpson@gmail.com>
To: "'Brian Cain'" <brian.cain@oss.qualcomm.com>, <qemu-devel@nongnu.org>
Cc: <richard.henderson@linaro.org>, <philmd@linaro.org>,
<quic_mathbern@quicinc.com>, <ale@rev.ng>, <anjo@rev.ng>,
<quic_mliebel@quicinc.com>, <alex.bennee@linaro.org>,
<quic_mburton@quicinc.com>, <sidneym@quicinc.com>,
"'Brian Cain'" <bcain@quicinc.com>
Subject: RE: [PATCH 20/38] target/hexagon: Implement do_raise_exception()
Date: Fri, 7 Mar 2025 15:28:56 -0600 [thread overview]
Message-ID: <02ab01db8fa7$efe738e0$cfb5aaa0$@gmail.com> (raw)
In-Reply-To: <20250301052628.1011210-21-brian.cain@oss.qualcomm.com>
> -----Original Message-----
> From: Brian Cain <brian.cain@oss.qualcomm.com>
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.cain@oss.qualcomm.com; richard.henderson@linaro.org;
> philmd@linaro.org; quic_mathbern@quicinc.com; ale@rev.ng; anjo@rev.ng;
> quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com;
> alex.bennee@linaro.org; quic_mburton@quicinc.com;
> sidneym@quicinc.com; Brian Cain <bcain@quicinc.com>
> Subject: [PATCH 20/38] target/hexagon: Implement do_raise_exception()
>
> From: Brian Cain <bcain@quicinc.com>
>
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index
> ccd806836c..1aa5b32b1f 100644
> --- a/target/hexagon/op_helper.c
> +++ b/target/hexagon/op_helper.c
> @@ -37,6 +37,26 @@
> #define SF_MANTBITS 23
>
> /* Exceptions processing helpers */
> +G_NORETURN
> +void do_raise_exception(CPUHexagonState *env, uint32_t exception,
> + target_ulong PC, uintptr_t retaddr) {
> + CPUState *cs = env_cpu(env);
> +#ifdef CONFIG_USER_ONLY
> + qemu_log_mask(CPU_LOG_INT, "%s: 0x%08x\n", __func__, exception);
> +#else
> + qemu_log_mask(CPU_LOG_INT, "%s: 0x%08x, @ %08" PRIx32 "\n",
> + __func__, exception, PC);
> +
> + ASSERT_DIRECT_TO_GUEST_UNSET(env, exception); #endif
> +
> + env->gpr[HEX_REG_PC] = PC;
> + cs->exception_index = exception;
> + cpu_loop_exit_restore(cs, retaddr);
> + cs->halted = false;
Shouldn't cs->halted be set before cpu_loop_exit_restore?
> +}
next prev parent reply other threads:[~2025-03-07 21:29 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-01 5:25 [PATCH 00/38] hexagon system emu, part 1/3 Brian Cain
2025-03-01 5:25 ` [PATCH 01/38] docs: Add hexagon sysemu docs Brian Cain
2025-03-05 19:29 ` ltaylorsimpson
2025-03-01 5:25 ` [PATCH 02/38] docs/system: Add hexagon CPU emulation Brian Cain
2025-03-05 19:36 ` ltaylorsimpson
2025-03-05 20:12 ` Brian Cain
2025-03-05 21:21 ` ltaylorsimpson
2025-03-05 21:28 ` Brian Cain
2025-03-01 5:25 ` [PATCH 03/38] target/hexagon: Add System/Guest register definitions Brian Cain
2025-03-06 20:54 ` ltaylorsimpson
2025-04-16 17:54 ` ltaylorsimpson
2025-04-16 19:43 ` Brian Cain
2025-04-16 22:02 ` ltaylorsimpson
2025-09-02 0:17 ` Brian Cain
2025-03-01 5:25 ` [PATCH 04/38] target/hexagon: Make gen_exception_end_tb non-static Brian Cain
2025-03-06 20:55 ` ltaylorsimpson
2025-03-01 5:25 ` [PATCH 05/38] target/hexagon: Switch to tag_ignore(), generate via get_{user, sys}_tags() Brian Cain via
2025-03-06 21:07 ` ltaylorsimpson
2025-03-01 5:25 ` [PATCH 06/38] target/hexagon: Add privilege check, use tag_ignore() Brian Cain
2025-03-06 21:11 ` ltaylorsimpson
2025-03-06 22:01 ` Richard Henderson
2025-09-02 0:24 ` Brian Cain
2025-03-01 5:25 ` [PATCH 07/38] target/hexagon: Add a placeholder fp exception Brian Cain
2025-03-06 21:22 ` ltaylorsimpson
2025-03-01 5:25 ` [PATCH 08/38] target/hexagon: Add guest, system reg number defs Brian Cain
2025-03-06 21:30 ` ltaylorsimpson
2025-03-08 0:35 ` Sid Manning
2025-09-02 0:25 ` Brian Cain
2025-03-01 5:25 ` [PATCH 09/38] target/hexagon: Add guest, system reg number state Brian Cain
2025-03-06 21:32 ` ltaylorsimpson
2025-03-12 19:15 ` Philippe Mathieu-Daudé
2025-09-02 0:27 ` Brian Cain
2025-03-01 5:26 ` [PATCH 10/38] target/hexagon: Add TCG values for sreg, greg Brian Cain
2025-03-06 21:38 ` ltaylorsimpson
2025-09-02 0:28 ` Brian Cain
2025-03-01 5:26 ` [PATCH 11/38] target/hexagon: Add guest/sys reg writes to DisasContext Brian Cain
2025-03-06 21:40 ` ltaylorsimpson
2025-03-01 5:26 ` [PATCH 12/38] target/hexagon: Add imported macro, attr defs for sysemu Brian Cain
2025-03-07 19:01 ` ltaylorsimpson
2025-09-02 0:36 ` Brian Cain
2025-03-01 5:26 ` [PATCH 13/38] target/hexagon: Define DCache states Brian Cain
2025-03-07 19:03 ` ltaylorsimpson
2025-03-01 5:26 ` [PATCH 14/38] target/hexagon: Add new macro definitions for sysemu Brian Cain
2025-03-07 19:35 ` ltaylorsimpson
2025-09-02 0:38 ` Brian Cain
2025-03-01 5:26 ` [PATCH 15/38] target/hexagon: Add handlers for guest/sysreg r/w Brian Cain
2025-03-07 19:46 ` ltaylorsimpson
2025-09-02 0:40 ` Brian Cain
2025-03-01 5:26 ` [PATCH 16/38] target/hexagon: Add placeholder greg/sreg r/w helpers Brian Cain
2025-03-07 20:45 ` ltaylorsimpson
2025-03-01 5:26 ` [PATCH 17/38] target/hexagon: Add vmstate representation Brian Cain
2025-03-07 21:19 ` ltaylorsimpson
2025-03-01 5:26 ` [PATCH 18/38] target/hexagon: Make A_PRIV, "J2_trap*" insts need_env() Brian Cain
2025-03-07 21:20 ` ltaylorsimpson
2025-03-01 5:26 ` [PATCH 19/38] target/hexagon: Define register fields for system regs Brian Cain
2025-03-07 21:21 ` ltaylorsimpson
2025-03-01 5:26 ` [PATCH 20/38] target/hexagon: Implement do_raise_exception() Brian Cain
2025-03-07 21:28 ` ltaylorsimpson [this message]
2025-09-02 0:41 ` Brian Cain
2025-03-01 5:26 ` [PATCH 21/38] target/hexagon: Add system reg insns Brian Cain
2025-03-08 1:32 ` ltaylorsimpson
2025-09-02 0:44 ` Brian Cain
2025-03-01 5:26 ` [PATCH 22/38] target/hexagon: Add sysemu TCG overrides Brian Cain
2025-03-08 1:43 ` ltaylorsimpson
2025-09-02 0:46 ` Brian Cain
2025-03-01 5:26 ` [PATCH 23/38] target/hexagon: Add implicit attributes to sysemu macros Brian Cain
2025-03-11 22:30 ` ltaylorsimpson
2025-09-02 0:47 ` Brian Cain
2025-03-01 5:26 ` [PATCH 24/38] target/hexagon: Add TCG overrides for int handler insts Brian Cain
2025-03-08 1:46 ` ltaylorsimpson
2025-03-01 5:26 ` [PATCH 25/38] target/hexagon: Add TCG overrides for thread ctl Brian Cain
2025-03-08 1:47 ` ltaylorsimpson
2025-03-01 5:26 ` [PATCH 26/38] target/hexagon: Add TCG overrides for rte, nmi Brian Cain
2025-03-11 22:33 ` ltaylorsimpson
2025-03-01 5:26 ` [PATCH 27/38] target/hexagon: Add sreg_{read,write} helpers Brian Cain
2025-03-11 23:22 ` ltaylorsimpson
2025-09-02 0:53 ` Brian Cain
2025-03-01 5:26 ` [PATCH 28/38] target/hexagon: Initialize htid, modectl regs Brian Cain
2025-03-11 23:26 ` ltaylorsimpson
2025-03-12 14:02 ` Sid Manning
2025-03-12 19:19 ` Philippe Mathieu-Daudé
2025-03-12 23:10 ` Brian Cain
2025-03-12 23:40 ` Philippe Mathieu-Daudé
2025-03-13 18:47 ` ltaylorsimpson
2025-03-13 19:06 ` Richard Henderson
2025-03-19 16:08 ` Sid Manning
2025-03-20 15:34 ` Richard Henderson
2025-03-20 17:38 ` Sid Manning
2025-09-02 0:56 ` Brian Cain
2025-03-01 5:26 ` [PATCH 29/38] target/hexagon: Add locks, id, next_PC to state Brian Cain
2025-03-11 23:33 ` ltaylorsimpson
2025-03-01 5:26 ` [PATCH 30/38] target/hexagon: Add a TLB count property Brian Cain
2025-03-11 23:41 ` ltaylorsimpson
2025-03-12 14:01 ` Sid Manning
2025-03-01 5:26 ` [PATCH 31/38] target/hexagon: Add {TLB, k0}lock, cause code, wait_next_pc Brian Cain via
2025-03-11 23:44 ` ltaylorsimpson
2025-03-12 16:58 ` [PATCH 31/38] target/hexagon: Add {TLB,k0}lock, " Sid Manning
2025-03-01 5:26 ` [PATCH 32/38] target/hexagon: Add stubs for modify_ssr/get_exe_mode Brian Cain
2025-03-11 23:43 ` ltaylorsimpson
2025-03-01 5:26 ` [PATCH 33/38] target/hexagon: Add gdb support for sys regs Brian Cain
2025-03-12 16:27 ` ltaylorsimpson
2025-03-12 19:10 ` Sid Manning
2025-03-12 19:27 ` Sid Manning
2025-03-12 19:46 ` Matheus Tavares Bernardino
2025-09-02 1:15 ` Brian Cain
2025-03-01 5:26 ` [PATCH 34/38] target/hexagon: Add initial MMU model Brian Cain
2025-03-12 17:04 ` ltaylorsimpson
2025-09-02 1:20 ` Brian Cain
2025-03-12 19:20 ` Philippe Mathieu-Daudé
2025-03-12 21:15 ` Sid Manning
2025-03-12 23:32 ` Philippe Mathieu-Daudé
2025-03-01 5:26 ` [PATCH 35/38] target/hexagon: Add IRQ events Brian Cain
2025-03-12 17:06 ` ltaylorsimpson
2025-03-01 5:26 ` [PATCH 36/38] target/hexagon: Add clear_wait_mode() definition Brian Cain
2025-03-12 17:08 ` ltaylorsimpson
2025-03-01 5:26 ` [PATCH 37/38] target/hexagon: Define f{S,G}ET_FIELD macros Brian Cain
2025-03-12 17:11 ` ltaylorsimpson
2025-03-01 5:26 ` [PATCH 38/38] target/hexagon: Add hex_interrupts support Brian Cain
2025-03-12 17:32 ` ltaylorsimpson
2025-09-02 1:22 ` Brian Cain
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='02ab01db8fa7$efe738e0$cfb5aaa0$@gmail.com' \
--to=ltaylorsimpson@gmail.com \
--cc=ale@rev.ng \
--cc=alex.bennee@linaro.org \
--cc=anjo@rev.ng \
--cc=bcain@quicinc.com \
--cc=brian.cain@oss.qualcomm.com \
--cc=philmd@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=quic_mathbern@quicinc.com \
--cc=quic_mburton@quicinc.com \
--cc=quic_mliebel@quicinc.com \
--cc=richard.henderson@linaro.org \
--cc=sidneym@quicinc.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).