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Wed, 19 Mar 2025 11:49:25 -0700 (PDT) Received: from DESKTOPUU50BPD ([2603:6000:a500:306:992d:4509:eca7:6f8]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6eade254502sm83477696d6.59.2025.03.19.11.49.24 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Mar 2025 11:49:25 -0700 (PDT) From: To: "'Brian Cain'" , Cc: , , , , , , , , References: <20250301052845.1012069-1-brian.cain@oss.qualcomm.com> <20250301052845.1012069-40-brian.cain@oss.qualcomm.com> In-Reply-To: <20250301052845.1012069-40-brian.cain@oss.qualcomm.com> Subject: RE: [PATCH 39/39] target/hexagon: Add pcycle setting functionality Date: Wed, 19 Mar 2025 13:49:23 -0500 Message-ID: <02cd01db98ff$a295cb90$e7c162b0$@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQIWUu77rEigiK0ljjjo9ZdCZqs5mQKFqcs0svEo52A= Content-Language: en-us X-Antivirus: Norton (VPS 250319-0, 3/18/2025), Outbound message X-Antivirus-Status: Clean Received-SPF: pass client-ip=2607:f8b0:4864:20::82d; envelope-from=ltaylorsimpson@gmail.com; helo=mail-qt1-x82d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org > -----Original Message----- > From: Brian Cain > Sent: Friday, February 28, 2025 11:29 PM > To: qemu-devel@nongnu.org > Cc: brian.cain@oss.qualcomm.com; richard.henderson@linaro.org; > philmd@linaro.org; quic_mathbern@quicinc.com; ale@rev.ng; anjo@rev.ng; > quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com; > alex.bennee@linaro.org; quic_mburton@quicinc.com; > sidneym@quicinc.com > Subject: [PATCH 39/39] target/hexagon: Add pcycle setting functionality > > Signed-off-by: Brian Cain > Signed-off-by: Matheus Tavares Bernardino > --- > target/hexagon/cpu.c | 10 +++++++--- > target/hexagon/cpu_helper.c | 17 ++++++++++++++--- > 2 files changed, 21 insertions(+), 6 deletions(-) > > diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index > 80f5e23794..4ca6add834 100644 > --- a/target/hexagon/cpu.c > +++ b/target/hexagon/cpu.c > @@ -440,19 +440,23 @@ static void hexagon_cpu_realize(DeviceState *dev, > Error **errp) #endif > > qemu_init_vcpu(cs); > -#ifndef CONFIG_USER_ONLY > CPUHexagonState *env = cpu_env(cs); > +#ifndef CONFIG_USER_ONLY > hex_mmu_realize(env); > if (cs->cpu_index == 0) { > env->g_sreg = g_new0(target_ulong, NUM_SREGS); > - env->g_pcycle_base = g_malloc0(sizeof(*env->g_pcycle_base)); > } else { > CPUState *cpu0 = qemu_get_cpu(0); > CPUHexagonState *env0 = cpu_env(cpu0); > env->g_sreg = env0->g_sreg; > - env->g_pcycle_base = env0->g_pcycle_base; > } > #endif > + if (cs->cpu_index == 0) { > + env->g_pcycle_base = g_malloc0(sizeof(*env->g_pcycle_base)); Another shared resource ... > + } else { > + CPUState *cpu0 = qemu_get_cpu(0); > + env->g_pcycle_base = cpu_env(cpu0)->g_pcycle_base; > + } > > mcc->parent_realize(dev, errp); > } > diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c > index 9c44cb7950..08c749e9fa 100644 > --- a/target/hexagon/cpu_helper.c > +++ b/target/hexagon/cpu_helper.c > @@ -70,18 +70,29 @@ uint32_t > hexagon_get_sys_pcycle_count_low(CPUHexagonState *env) void > hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, > uint32_t cycles_hi) > { > - g_assert_not_reached(); > + uint64_t cur_cycles = hexagon_get_sys_pcycle_count(env); > + uint64_t cycles = > + ((uint64_t)cycles_hi << 32) | extract64(cur_cycles, 0, 32); > + hexagon_set_sys_pcycle_count(env, cycles); > } > > void hexagon_set_sys_pcycle_count_low(CPUHexagonState *env, > uint32_t cycles_lo) > { > - g_assert_not_reached(); > + uint64_t cur_cycles = hexagon_get_sys_pcycle_count(env); > + uint64_t cycles = extract64(cur_cycles, 32, 32) | cycles_lo; > + hexagon_set_sys_pcycle_count(env, cycles); > } > > void hexagon_set_sys_pcycle_count(CPUHexagonState *env, uint64_t > cycles) { > - g_assert_not_reached(); Do we need a lock here? > + *(env->g_pcycle_base) = cycles; > + > + CPUState *cs; > + CPU_FOREACH(cs) { > + CPUHexagonState *env_ = cpu_env(cs); This underscore is easy to miss. Just cpu_env(cs)->t_cycle_count = 0;