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Content-Language: en-US To: Richard Henderson , Chinmay Rath , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, npiggin@gmail.com, danielhb413@gmail.com, harshpb@linux.ibm.com References: <20240416063927.99428-1-rathc@linux.ibm.com> <20240416063927.99428-3-rathc@linux.ibm.com> From: Chinmay Rath In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: -CNB9WZ_DU_GeJfmCDZYcR1yd19jtkj7 X-Proofpoint-GUID: S7mGG3DuznqfYS-rdsZxNcDPP-OxGlaz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-19_06,2024-04-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 suspectscore=0 mlxscore=0 malwarescore=0 spamscore=0 adultscore=0 clxscore=1015 impostorscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=729 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2404010000 definitions=main-2404190068 Received-SPF: none client-ip=148.163.158.5; envelope-from=rathc@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Richard, On 4/16/24 23:27, Richard Henderson wrote: > On 4/15/24 23:39, Chinmay Rath wrote: >> The handler methods for divw[u] instructions internally use >> Rc(ctx->opcode), >> for extraction of Rc field of instructions, which poses a problem if >> we move >> the above said instructions to decodetree, as the ctx->opcode field >> is not >> popluated in decodetree. Hence, making it decodetree compatible, so >> that the >> mentioned insns can be safely move to decodetree specs. >> >> Signed-off-by: Chinmay Rath >> --- >>   target/ppc/translate.c | 9 +++++---- >>   1 file changed, 5 insertions(+), 4 deletions(-) > > Reviewed-by: Richard Henderson > Thank you. >> +static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, >> +                                     TCGv arg1, TCGv arg2, bool sign, >> +                                     bool compute_ov, bool compute_rc0) > > Could drop the inline at the same time. > Let the compiler decide. > I kept inline as is, as there are multiple gen_op_* routines with inline and if necessary we could consider removing inline for all of them together in a separate patch : grep inline target/ppc/translate.c | grep gen_op static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, static inline void gen_op_arith_compute_ca32(DisasContext *ctx, static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, static inline void gen_op_mfspr(DisasContext *ctx) Thanks, Chinmay > > r~