From: Richard Henderson <rth@twiddle.net>
To: Michael Rolnik <mrolnik@gmail.com>, qemu-devel@nongnu.org
Cc: Michael Rolnik <rolnik@amazon.com>
Subject: Re: [Qemu-devel] [PATCH 09/10] target-avr: updating translate.c to use instructions translation
Date: Sat, 4 Jun 2016 20:33:30 -0700 [thread overview]
Message-ID: <02f74c6c-164d-5fb9-f904-2ba3e4a819b6@twiddle.net> (raw)
In-Reply-To: <1464898022-97990-9-git-send-email-rolnik@amazon.com>
On 06/02/2016 01:07 PM, Michael Rolnik wrote:
> +uint32_t get_opcode(
> + uint8_t const *code,
> + unsigned bitBase,
> + unsigned bitSize)
> +{
> + return *(uint16_t *)code;
> +}
Unused. And what was this supposed to do?
> + /* decode next instruction */
> + ctx.inst[1].cpc = ctx.inst[0].npc;
> + decode_opc(cpu, &ctx, &ctx.inst[1]);
Why are you decoding one instruction ahead?
While I can see that this might be keen for some of the skip-next instructions,
I don't see that you're using that just now. So perhaps delay this until it's
actually used?
r~
next prev parent reply other threads:[~2016-06-05 3:33 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-02 20:06 [Qemu-devel] [PATCH 01/10] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions Michael Rolnik
2016-06-02 20:06 ` [Qemu-devel] [PATCH 02/10] target-avr: adding AVR CPU features/flavors Michael Rolnik
2016-06-04 20:02 ` Richard Henderson
2016-06-02 20:06 ` [Qemu-devel] [PATCH 03/10] target-avr: adding a sample AVR board Michael Rolnik
2016-06-02 20:06 ` [Qemu-devel] [PATCH 04/10] target-avr: adding instructions encodings Michael Rolnik
2016-06-04 22:17 ` Richard Henderson
2016-06-05 5:09 ` Michael Rolnik
2016-06-05 16:08 ` Richard Henderson
2016-06-02 20:06 ` [Qemu-devel] [PATCH 05/10] target-avr: adding AVR interrupt handling Michael Rolnik
2016-06-04 22:26 ` Richard Henderson
2016-06-05 5:10 ` Michael Rolnik
2016-06-02 20:06 ` [Qemu-devel] [PATCH 06/10] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions Michael Rolnik
2016-06-04 22:48 ` Richard Henderson
2016-06-05 5:10 ` Michael Rolnik
2016-06-02 20:06 ` [Qemu-devel] [PATCH 07/10] target-avr: adding instruction decoder Michael Rolnik
2016-06-04 23:00 ` Richard Henderson
2016-06-05 5:18 ` Michael Rolnik
2016-06-02 20:07 ` [Qemu-devel] [PATCH 08/10] target-avr: adding instruction translation Michael Rolnik
2016-06-05 3:27 ` Richard Henderson
2016-06-05 21:47 ` Michael Rolnik
2016-06-05 23:34 ` Richard Henderson
2016-06-06 6:52 ` Michael Rolnik
2016-06-06 19:17 ` Richard Henderson
2016-06-06 19:34 ` Michael Rolnik
2016-06-02 20:07 ` [Qemu-devel] [PATCH 09/10] target-avr: updating translate.c to use instructions translation Michael Rolnik
2016-06-05 3:33 ` Richard Henderson [this message]
2016-06-05 21:49 ` Michael Rolnik
2016-06-02 20:07 ` [Qemu-devel] [PATCH 10/10] target-avr: fixing code style Michael Rolnik
2016-06-02 23:10 ` Peter Maydell
2016-06-04 17:41 ` Richard Henderson
2016-06-04 18:34 ` Michael Rolnik
2016-06-04 22:33 ` Richard Henderson
2016-06-05 12:27 ` Peter Maydell
2016-06-05 3:34 ` Richard Henderson
2016-06-04 19:55 ` [Qemu-devel] [PATCH 01/10] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions Richard Henderson
-- strict thread matches above, loose matches on Subject: below --
2016-06-02 20:03 Michael Rolnik
2016-06-02 20:04 ` [Qemu-devel] [PATCH 09/10] target-avr: updating translate.c to use instructions translation Michael Rolnik
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