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envelope-from=ltaylorsimpson@gmail.com; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org > -----Original Message----- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.cain@oss.qualcomm.com; richard.henderson@linaro.org; > philmd@linaro.org; quic_mathbern@quicinc.com; ale@rev.ng; anjo@rev.ng; > quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com; > alex.bennee@linaro.org; quic_mburton@quicinc.com; > sidneym@quicinc.com; Brian Cain > Subject: [PATCH 22/38] target/hexagon: Add sysemu TCG overrides > > From: Brian Cain > > Define TCG overrides for setprio(), crswap(,sgp{0,1,1:0}). > > Signed-off-by: Brian Cain > --- > target/hexagon/cpu_helper.h | 32 ++++++++++++++++++++++++++++ > target/hexagon/gen_tcg_sys.h | 41 > ++++++++++++++++++++++++++++++++++++ > target/hexagon/helper.h | 1 + > target/hexagon/cpu_helper.c | 36 +++++++++++++++++++++++++++++++ > target/hexagon/genptr.c | 4 ++++ > target/hexagon/op_helper.c | 7 ++++++ > target/hexagon/hex_common.py | 2 ++ > target/hexagon/meson.build | 14 ++++++------ > 8 files changed, 131 insertions(+), 6 deletions(-) create mode 100644 > target/hexagon/cpu_helper.h create mode 100644 > target/hexagon/gen_tcg_sys.h create mode 100644 > target/hexagon/cpu_helper.c > > diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h > new file mode 100644 index 0000000000..194bcbf451 > --- /dev/null > +++ b/target/hexagon/cpu_helper.h > @@ -0,0 +1,32 @@ > +/* > + * Copyright(c) 2019-2025 Qualcomm Innovation Center, Inc. All Rights > Reserved. > + * > + * SPDX-License-Identifier: GPL-2.0-or-later */ > + > +#ifndef HEXAGON_CPU_HELPER_H > +#define HEXAGON_CPU_HELPER_H > + > +static inline void arch_set_thread_reg(CPUHexagonState *env, uint32_t > reg, > + uint32_t val) { > + g_assert(reg < TOTAL_PER_THREAD_REGS); > + g_assert_not_reached(); > +} > + > +static inline uint32_t arch_get_thread_reg(CPUHexagonState *env, > +uint32_t reg) { > + g_assert(reg < TOTAL_PER_THREAD_REGS); > + g_assert_not_reached(); > +} > + > +static inline void arch_set_system_reg(CPUHexagonState *env, uint32_t > reg, > + uint32_t val) { > + g_assert_not_reached(); > +} > + > +uint32_t arch_get_system_reg(CPUHexagonState *env, uint32_t reg); > + > +#endif > + > diff --git a/target/hexagon/gen_tcg_sys.h b/target/hexagon/gen_tcg_sys.h > new file mode 100644 index 0000000000..362703ab45 > --- /dev/null > +++ b/target/hexagon/gen_tcg_sys.h > @@ -0,0 +1,41 @@ > +/* > + * Copyright(c) 2022-2025 Qualcomm Innovation Center, Inc. All Rights > Reserved. > + * > + * SPDX-License-Identifier: GPL-2.0-or-later */ > + > +#ifndef HEXAGON_GEN_TCG_SYS_H > +#define HEXAGON_GEN_TCG_SYS_H > + > +#define fGEN_TCG_Y2_setprio(SHORTCODE) \ > + gen_helper_setprio(tcg_env, PtV, RsV) > + > +#define fGEN_TCG_Y2_crswap0(SHORTCODE) \ > + do { \ > + TCGv tmp = tcg_temp_new(); \ > + tcg_gen_mov_tl(tmp, RxV); \ > + tcg_gen_mov_tl(RxV, hex_t_sreg[HEX_SREG_SGP0]); \ > + tcg_gen_mov_tl(ctx->t_sreg_new_value[HEX_SREG_SGP0], tmp); \ > + } while (0) > + > +#define fGEN_TCG_Y4_crswap1(SHORTCODE) \ > + do { \ > + TCGv tmp = tcg_temp_new(); \ > + tcg_gen_mov_tl(tmp, RxV); \ > + tcg_gen_mov_tl(RxV, hex_t_sreg[HEX_SREG_SGP1]); \ > + tcg_gen_mov_tl(ctx->t_sreg_new_value[HEX_SREG_SGP1], tmp); \ > + } while (0) > + > +#define fGEN_TCG_Y4_crswap10(SHORTCODE) \ > + do { \ > + g_assert_not_reached(); \ > + TCGv_i64 tmp = tcg_temp_new_i64(); \ > + tcg_gen_mov_i64(tmp, RxxV); \ > + tcg_gen_concat_i32_i64(RxxV, \ > + hex_t_sreg[HEX_SREG_SGP0], \ > + hex_t_sreg[HEX_SREG_SGP1]); \ > + tcg_gen_extrl_i64_i32(ctx->t_sreg_new_value[HEX_SREG_SGP0], > tmp); \ > + tcg_gen_extrh_i64_i32(ctx->t_sreg_new_value[HEX_SREG_SGP1], > tmp); \ > + } while (0) > + > +#endif > diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index > fddbd99a19..146f4f02e4 100644 > --- a/target/hexagon/helper.h > +++ b/target/hexagon/helper.h > @@ -115,4 +115,5 @@ DEF_HELPER_2(greg_read, i32, env, i32) > DEF_HELPER_2(greg_read_pair, i64, env, i32) DEF_HELPER_3(sreg_write, > void, env, i32, i32) DEF_HELPER_3(sreg_write_pair, void, env, i32, i64) > +DEF_HELPER_3(setprio, void, env, i32, i32) > #endif > diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c > new file mode 100644 index 0000000000..6e4bc85580 > --- /dev/null > +++ b/target/hexagon/cpu_helper.c > @@ -0,0 +1,36 @@ > +/* > + * Copyright(c) 2019-2025 Qualcomm Innovation Center, Inc. All Rights > Reserved. > + * > + * SPDX-License-Identifier: GPL-2.0-or-later */ > + > +#include "qemu/osdep.h" > +#include "cpu.h" > +#include "cpu_helper.h" > +#include "system/cpus.h" > +#ifdef CONFIG_USER_ONLY > +#include "qemu.h" > +#include "exec/helper-proto.h" > +#else > +#include "hw/boards.h" > +#include "hw/hexagon/hexagon.h" > +#endif > +#include "exec/exec-all.h" > +#include "exec/cpu_ldst.h" > +#include "qemu/log.h" > +#include "tcg/tcg-op.h" > +#include "internal.h" > +#include "macros.h" > +#include "sys_macros.h" > +#include "arch.h" > + > + > +#ifndef CONFIG_USER_ONLY > + > +uint32_t arch_get_system_reg(CPUHexagonState *env, uint32_t reg) { > + g_assert_not_reached(); > +} This should be a static inline in cpu_helper.h. That means you could postpone the introduction of this new file. Otherwise Reviewed-by: Taylor Simpson