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Wed, 16 Apr 2025 11:58:24 -0700 (PDT) Received: from [192.168.1.87] ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73bd2198d95sm11153682b3a.17.2025.04.16.11.58.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Apr 2025 11:58:24 -0700 (PDT) Message-ID: <032b035e-cb83-4d2b-b67c-8f4dd9a511b4@linaro.org> Date: Wed, 16 Apr 2025 11:58:14 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 121/163] tcg/i386: Remove support for add2/sub2 Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20250415192515.232910-1-richard.henderson@linaro.org> <20250415192515.232910-122-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20250415192515.232910-122-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/15/25 12:24, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/i386/tcg-target-con-set.h | 1 - > tcg/i386/tcg-target-has.h | 8 ++++---- > tcg/i386/tcg-target.c.inc | 31 ------------------------------- > 3 files changed, 4 insertions(+), 36 deletions(-) > > diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-target-con-set.h > index 0ae9775944..85c93836bb 100644 > --- a/tcg/i386/tcg-target-con-set.h > +++ b/tcg/i386/tcg-target-con-set.h > @@ -57,4 +57,3 @@ C_O2_I1(r, r, L) > C_O2_I2(a, d, a, r) > C_O2_I2(r, r, L, L) > C_O2_I3(a, d, 0, 1, r) > -C_N1_O1_I4(r, r, 0, 1, re, re) > diff --git a/tcg/i386/tcg-target-has.h b/tcg/i386/tcg-target-has.h > index 0328102c2a..a984a6af2e 100644 > --- a/tcg/i386/tcg-target-has.h > +++ b/tcg/i386/tcg-target-has.h > @@ -26,14 +26,14 @@ > #define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512vl) > > /* optional instructions */ > -#define TCG_TARGET_HAS_add2_i32 1 > -#define TCG_TARGET_HAS_sub2_i32 1 > +#define TCG_TARGET_HAS_add2_i32 0 > +#define TCG_TARGET_HAS_sub2_i32 0 > > #if TCG_TARGET_REG_BITS == 64 > /* Keep 32-bit values zero-extended in a register. */ > #define TCG_TARGET_HAS_extr_i64_i32 1 > -#define TCG_TARGET_HAS_add2_i64 1 > -#define TCG_TARGET_HAS_sub2_i64 1 > +#define TCG_TARGET_HAS_add2_i64 0 > +#define TCG_TARGET_HAS_sub2_i64 0 > #define TCG_TARGET_HAS_qemu_st8_i32 0 > #else > #define TCG_TARGET_HAS_qemu_st8_i32 1 > diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc > index 52d3402f29..44f9afc0d6 100644 > --- a/tcg/i386/tcg-target.c.inc > +++ b/tcg/i386/tcg-target.c.inc > @@ -3479,31 +3479,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I128); > break; > > - OP_32_64(add2): > - if (const_args[4]) { > - tgen_arithi(s, ARITH_ADD + rexw, a0, args[4], 1); > - } else { > - tgen_arithr(s, ARITH_ADD + rexw, a0, args[4]); > - } > - if (const_args[5]) { > - tgen_arithi(s, ARITH_ADC + rexw, a1, args[5], 1); > - } else { > - tgen_arithr(s, ARITH_ADC + rexw, a1, args[5]); > - } > - break; > - OP_32_64(sub2): > - if (const_args[4]) { > - tgen_arithi(s, ARITH_SUB + rexw, a0, args[4], 1); > - } else { > - tgen_arithr(s, ARITH_SUB + rexw, a0, args[4]); > - } > - if (const_args[5]) { > - tgen_arithi(s, ARITH_SBB + rexw, a1, args[5], 1); > - } else { > - tgen_arithr(s, ARITH_SBB + rexw, a1, args[5]); > - } > - break; > - > #if TCG_TARGET_REG_BITS == 64 > case INDEX_op_ld32s_i64: > tcg_out_modrm_offset(s, OPC_MOVSLQ, a0, a1, a2); > @@ -4109,12 +4084,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > case INDEX_op_st_i64: > return C_O0_I2(re, r); > > - case INDEX_op_add2_i32: > - case INDEX_op_add2_i64: > - case INDEX_op_sub2_i32: > - case INDEX_op_sub2_i64: > - return C_N1_O1_I4(r, r, 0, 1, re, re); > - > case INDEX_op_qemu_ld_i32: > return C_O1_I1(r, L); > Reviewed-by: Pierrick Bouvier