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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b66363fsm16294530f8f.36.2025.04.01.20.50.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Apr 2025 20:50:18 -0700 (PDT) Message-ID: <03556e83-472c-4ac1-910d-bff29fa3ba58@linaro.org> Date: Wed, 2 Apr 2025 05:50:17 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH-for-10.1 23/24] hw/core/cpu: Remove CPUClass::mmu_index() To: qemu-devel@nongnu.org Cc: Gustavo Romero , Pierrick Bouvier , Paolo Bonzini , Richard Henderson References: <20250401080938.32278-1-philmd@linaro.org> <20250401080938.32278-24-philmd@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250401080938.32278-24-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/4/25 10:09, Philippe Mathieu-Daudé wrote: > All targets have been converted to TCGCPUOps::mmu_index(), > remove the now unused CPUClass::mmu_index(). > > Signed-off-by: Philippe Mathieu-Daudé > --- > include/exec/cpu-mmu-index.h | 4 +--- > include/hw/core/cpu.h | 2 -- > 2 files changed, 1 insertion(+), 5 deletions(-) > > diff --git a/include/exec/cpu-mmu-index.h b/include/exec/cpu-mmu-index.h > index 651526e9f97..a87b6f7c4b7 100644 > --- a/include/exec/cpu-mmu-index.h > +++ b/include/exec/cpu-mmu-index.h > @@ -32,9 +32,7 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch) > # endif > #endif > > - const TCGCPUOps *tcg_ops = cs->cc->tcg_ops; > - int ret = tcg_ops->mmu_index ? tcg_ops->mmu_index(cs, ifetch) > - : cs->cc->mmu_index(cs, ifetch); > + int ret = cs->cc->tcg_ops->mmu_index(cs, ifetch); > tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES); > return ret; > } > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h > index 60b7abaf49b..10b6b25b344 100644 > --- a/include/hw/core/cpu.h > +++ b/include/hw/core/cpu.h > @@ -104,7 +104,6 @@ struct SysemuCPUOps; > * instantiatable CPU type. > * @parse_features: Callback to parse command line arguments. > * @reset_dump_flags: #CPUDumpFlags to use for reset logging. > - * @mmu_index: Callback for choosing softmmu mmu index. > * @memory_rw_debug: Callback for GDB memory access. > * @dump_state: Callback for dumping state. > * @query_cpu_fast: > @@ -151,7 +150,6 @@ struct CPUClass { > ObjectClass *(*class_by_name)(const char *cpu_model); > void (*parse_features)(const char *typename, char *str, Error **errp); > > - int (*mmu_index)(CPUState *cpu, bool ifetch); > int (*memory_rw_debug)(CPUState *cpu, vaddr addr, > uint8_t *buf, size_t len, bool is_write); > void (*dump_state)(CPUState *cpu, FILE *, int flags); And I'll squash: -- >8 -- diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8057a5a0ce8..b00f046b29f 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -1077,6 +1077,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) assert(tcg_ops->cpu_exec_interrupt); #endif /* !CONFIG_USER_ONLY */ assert(tcg_ops->translate_code); + assert(tcg_ops->mmu_index); tcg_ops->initialize(); tcg_target_initialized = true; } ---