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([2602:ae:154a:9f01:7632:29c7:3cce:bec3]) by smtp.gmail.com with ESMTPSA id x7-20020a1709029a4700b0019abb539cddsm7121848plv.10.2023.03.06.12.22.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Mar 2023 12:22:54 -0800 (PST) Message-ID: <035eeedd-9bba-43f1-2f19-2b51cec2d846@linaro.org> Date: Mon, 6 Mar 2023 12:22:52 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [Qemu-devel] [PULL 11/29] target/riscv: Convert RV32F insns to decodetree Content-Language: en-US To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Palmer Dabbelt , Bastian Koppelmann Cc: Peter Maydell , Peer Adelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis References: <20190312131526.14710-1-palmer@sifive.com> <20190312131526.14710-12-palmer@sifive.com> <69d3e5e4-a563-61a6-c3e0-8a6ef026ac8f@linaro.org> From: Richard Henderson In-Reply-To: <69d3e5e4-a563-61a6-c3e0-8a6ef026ac8f@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/6/23 06:11, Philippe Mathieu-Daudé wrote: > Hi Palmer, Bastian, > > (old patch) > > On 12/3/19 14:15, Palmer Dabbelt wrote: >> From: Bastian Koppelmann >> >> Acked-by: Alistair Francis >> Reviewed-by: Richard Henderson >> Signed-off-by: Bastian Koppelmann >> Signed-off-by: Peer Adelt >> Signed-off-by: Palmer Dabbelt >> --- >>   target/riscv/insn32.decode              |  35 +++ >>   target/riscv/insn_trans/trans_rvf.inc.c | 379 ++++++++++++++++++++++++ >>   target/riscv/translate.c                |   1 + >>   3 files changed, 415 insertions(+) >>   create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c > > >> +static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a) >> +{ >> +    /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */ >> +    REQUIRE_FPU; >> +    REQUIRE_EXT(ctx, RVF); >> + >> +    TCGv t0 = tcg_temp_new(); >> + >> +#if defined(TARGET_RISCV64) > > Just noticed this while reviewing Richard's "tcg: Remove tcg_const_*' > recent series, shouldn't be this #if condition inverted? No, you'd notice the compile error straight away. r~ > >> +    tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]); >> +#else >> +    tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]); >> +#endif >> + >> +    gen_set_gpr(a->rd, t0); >> +    tcg_temp_free(t0); >> + >> +    return true; >> +} > >