[PULL 00/33] target-arm queue

[PULL 00/33] target-arm queue

[Peter Maydell]

Another arm pullreq; nothing particularly exciting here.

-- PMM


The following changes since commit e27d5b488ef08408691bfed61f34ee2858136287:

  Merge remote-tracking branch 'remotes/juanquintela/tags/pull-migration-pull-request' into staging (2020-02-28 14:02:31 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200228

for you to fetch changes up to 1904f9b5f1d94fe12fe021db6b504c87d684f6db:

  hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2 (2020-02-28 16:14:57 +0000)

----------------------------------------------------------------
target-arm queue:
 * hw/arm: Use TYPE_PL011 to create serial port
 * target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn
 * hw/arm/integratorcp: Map the audio codec controller
 * GICv2: Correctly implement the limited number of priority bits
 * target/arm: refactoring of VFP related feature checks and decode
 * xilinx_zynq: Fix USB port instantiation
 * acceptance tests for n800, n810, integratorcp
 * Implement v8.3-RCPC, v8.4-RCPC, v8.3-CCIDX
 * arm_gic_kvm: Don't assume kernel can provide a GICv2
   (provide better error message for user error)

----------------------------------------------------------------
Gavin Shan (1):
      hw/arm: Use TYPE_PL011 to create serial port

Guenter Roeck (2):
      hw/arm/xilinx_zynq: Fix USB port instantiation
      hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class

Peter Maydell (5):
      target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0
      target/arm: Implement v8.3-RCPC
      target/arm: Implement v8.4-RCPC
      target/arm: Implement ARMv8.3-CCIDX
      hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2

Philippe Mathieu-Daudé (3):
      hw/arm/integratorcp: Map the audio codec controller
      tests/acceptance: Extract boot_integratorcp() from test_integratorcp()
      tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer

Richard Henderson (17):
      target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn
      target/arm: Add isar_feature_aa32_vfp_simd
      target/arm: Rename isar_feature_aa32_fpdp_v2
      target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}
      target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp
      target/arm: Perform fpdp_v2 check first
      target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3
      target/arm: Add missing checks for fpsp_v2
      target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac
      target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn
      target/arm: Move VLLDM and VLSTM to vfp.decode
      target/arm: Move the vfp decodetree calls next to the base isa
      linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP
      target/arm: Remove ARM_FEATURE_VFP*
      target/arm: Add formats for some vfp 2 and 3-register insns
      target/arm: Split VFM decode
      target/arm: Split VMINMAXNM decode

Sai Pavan Boddu (3):
      arm_gic: Mask the un-supported priority bits
      cpu/a9mpcore: Set number of GIC priority bits to 5
      cpu/arm11mpcore: Set number of GIC priority bits to 4

Thomas Huth (2):
      tests/acceptance: Add a test for the N800 and N810 arm machines
      tests/acceptance: Add a test for the integratorcp arm machine

 include/hw/intc/arm_gic.h                    |   2 +
 include/hw/intc/arm_gic_common.h             |   1 +
 target/arm/cpu.h                             |  88 +++++-
 hw/arm/integratorcp.c                        |   1 +
 hw/arm/sbsa-ref.c                            |   3 +-
 hw/arm/virt.c                                |   3 +-
 hw/arm/xilinx_zynq.c                         |   5 +-
 hw/arm/xlnx-versal.c                         |   3 +-
 hw/cpu/a9mpcore.c                            |   4 +
 hw/cpu/arm11mpcore.c                         |   5 +
 hw/intc/arm_gic.c                            |  33 +-
 hw/intc/arm_gic_common.c                     |   1 +
 hw/intc/arm_gic_kvm.c                        |   9 +
 hw/intc/armv7m_nvic.c                        |  20 +-
 hw/usb/hcd-ehci-sysbus.c                     |  17 -
 linux-user/arm/signal.c                      |   4 +-
 linux-user/elfload.c                         |  25 +-
 target/arm/arch_dump.c                       |  11 +-
 target/arm/cpu.c                             |  44 +--
 target/arm/cpu64.c                           |   5 +-
 target/arm/helper.c                          |  23 +-
 target/arm/kvm32.c                           |   5 -
 target/arm/kvm64.c                           |   1 -
 target/arm/m_helper.c                        |  11 +-
 target/arm/machine.c                         |   5 +-
 target/arm/translate-a64.c                   | 114 +++++++
 target/arm/translate-vfp.inc.c               | 448 +++++++++++++++++----------
 target/arm/translate.c                       | 122 ++------
 MAINTAINERS                                  |   2 +
 hw/arm/Kconfig                               |   1 +
 target/arm/vfp-uncond.decode                 |  12 +-
 target/arm/vfp.decode                        | 153 ++++-----
 tests/acceptance/machine_arm_integratorcp.py |  99 ++++++
 tests/acceptance/machine_arm_n8x0.py         |  49 +++
 34 files changed, 865 insertions(+), 464 deletions(-)
 create mode 100644 tests/acceptance/machine_arm_integratorcp.py
 create mode 100644 tests/acceptance/machine_arm_n8x0.py

Re: [PULL 00/33] target-arm queue

[Peter Maydell]

On Fri, 28 Feb 2020 at 16:38, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Another arm pullreq; nothing particularly exciting here.
>
> -- PMM
>
>
> The following changes since commit e27d5b488ef08408691bfed61f34ee2858136287:
>
>   Merge remote-tracking branch 'remotes/juanquintela/tags/pull-migration-pull-request' into staging (2020-02-28 14:02:31 +0000)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200228
>
> for you to fetch changes up to 1904f9b5f1d94fe12fe021db6b504c87d684f6db:
>
>   hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2 (2020-02-28 16:14:57 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * hw/arm: Use TYPE_PL011 to create serial port
>  * target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn
>  * hw/arm/integratorcp: Map the audio codec controller
>  * GICv2: Correctly implement the limited number of priority bits
>  * target/arm: refactoring of VFP related feature checks and decode
>  * xilinx_zynq: Fix USB port instantiation
>  * acceptance tests for n800, n810, integratorcp
>  * Implement v8.3-RCPC, v8.4-RCPC, v8.3-CCIDX
>  * arm_gic_kvm: Don't assume kernel can provide a GICv2
>    (provide better error message for user error)


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.

-- PMM

[PULL 00/33] target-arm queue

[Peter Maydell]

Arm pullreq: Rémi's ARMv8.4-SEL2 support is the big thing here.

thanks
-- PMM

The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:

  Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119

for you to fetch changes up to 6d39956891b3d1857af84f72f0230a6d99eb3b6a:

  docs: Build and install all the docs in a single manual (2021-01-19 14:38:53 +0000)

----------------------------------------------------------------
target-arm queue:
 * Implement IMPDEF pauth algorithm
 * Support ARMv8.4-SEL2
 * Fix bug where we were truncating predicate vector lengths in SVE insns
 * Implement new pvpanic-pci device
 * npcm7xx_adc-test: Fix memleak in adc_qom_set
 * target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
 * docs: Build and install all the docs in a single manual

----------------------------------------------------------------
Gan Qixin (1):
      npcm7xx_adc-test: Fix memleak in adc_qom_set

Mihai Carabas (4):
      hw/misc/pvpanic: split-out generic and bus dependent code
      hw/misc/pvpanic: add PCI interface support
      pvpanic : update pvpanic spec document
      tests/qtest: add a test case for pvpanic-pci

Peter Maydell (1):
      docs: Build and install all the docs in a single manual

Philippe Mathieu-Daudé (1):
      target/arm/m_helper: Silence GCC 10 maybe-uninitialized error

Richard Henderson (7):
      target/arm: Implement an IMPDEF pauth algorithm
      target/arm: Add cpu properties to control pauth
      target/arm: Use object_property_add_bool for "sve" property
      target/arm: Introduce PREDDESC field definitions
      target/arm: Update PFIRST, PNEXT for pred_desc
      target/arm: Update ZIP, UZP, TRN for pred_desc
      target/arm: Update REV, PUNPK for pred_desc

Rémi Denis-Courmont (19):
      target/arm: remove redundant tests
      target/arm: add arm_is_el2_enabled() helper
      target/arm: use arm_is_el2_enabled() where applicable
      target/arm: use arm_hcr_el2_eff() where applicable
      target/arm: factor MDCR_EL2 common handling
      target/arm: Define isar_feature function to test for presence of SEL2
      target/arm: add 64-bit S-EL2 to EL exception table
      target/arm: add MMU stage 1 for Secure EL2
      target/arm: add ARMv8.4-SEL2 system registers
      target/arm: handle VMID change in secure state
      target/arm: do S1_ptw_translate() before address space lookup
      target/arm: translate NS bit in page-walks
      target/arm: generalize 2-stage page-walk condition
      target/arm: secure stage 2 translation regime
      target/arm: set HPFAR_EL2.NS on secure stage 2 faults
      target/arm: revector to run-time pick target EL
      target/arm: Implement SCR_EL2.EEL2
      target/arm: enable Secure EL2 in max CPU
      target/arm: refactor vae1_tlbmask()

 docs/conf.py                     |  46 ++++-
 docs/devel/conf.py               |  15 --
 docs/index.html.in               |  17 --
 docs/interop/conf.py             |  28 ---
 docs/meson.build                 |  64 +++---
 docs/specs/conf.py               |  16 --
 docs/specs/pci-ids.txt           |   1 +
 docs/specs/pvpanic.txt           |  13 +-
 docs/system/arm/cpu-features.rst |  21 ++
 docs/system/conf.py              |  28 ---
 docs/tools/conf.py               |  37 ----
 docs/user/conf.py                |  15 --
 include/hw/misc/pvpanic.h        |  24 ++-
 include/hw/pci/pci.h             |   1 +
 include/qemu/xxhash.h            |  98 +++++++++
 target/arm/cpu-param.h           |   2 +-
 target/arm/cpu.h                 | 107 ++++++++--
 target/arm/internals.h           |  45 +++++
 hw/misc/pvpanic-isa.c            |  94 +++++++++
 hw/misc/pvpanic-pci.c            |  95 +++++++++
 hw/misc/pvpanic.c                |  85 +-------
 target/arm/cpu.c                 |  23 ++-
 target/arm/cpu64.c               |  65 ++++--
 target/arm/helper-a64.c          |   8 +-
 target/arm/helper.c              | 414 ++++++++++++++++++++++++++-------------
 target/arm/m_helper.c            |   2 +-
 target/arm/monitor.c             |   1 +
 target/arm/op_helper.c           |   4 +-
 target/arm/pauth_helper.c        |  27 ++-
 target/arm/sve_helper.c          |  33 ++--
 target/arm/tlb_helper.c          |   3 +
 target/arm/translate-a64.c       |   4 +
 target/arm/translate-sve.c       |  31 ++-
 target/arm/translate.c           |  36 +++-
 tests/qtest/arm-cpu-features.c   |  13 ++
 tests/qtest/npcm7xx_adc-test.c   |   1 +
 tests/qtest/pvpanic-pci-test.c   |  62 ++++++
 .gitlab-ci.yml                   |   4 +-
 hw/i386/Kconfig                  |   2 +-
 hw/misc/Kconfig                  |  12 +-
 hw/misc/meson.build              |   4 +-
 tests/qtest/meson.build          |   3 +-
 42 files changed, 1080 insertions(+), 524 deletions(-)
 delete mode 100644 docs/devel/conf.py
 delete mode 100644 docs/index.html.in
 delete mode 100644 docs/interop/conf.py
 delete mode 100644 docs/specs/conf.py
 delete mode 100644 docs/system/conf.py
 delete mode 100644 docs/tools/conf.py
 delete mode 100644 docs/user/conf.py
 create mode 100644 hw/misc/pvpanic-isa.c
 create mode 100644 hw/misc/pvpanic-pci.c
 create mode 100644 tests/qtest/pvpanic-pci-test.c

Re: [PULL 00/33] target-arm queue

[no-reply]

Patchew URL: https://patchew.org/QEMU/20210119151104.16264-1-peter.maydell@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210119151104.16264-1-peter.maydell@linaro.org
Subject: [PULL 00/33] target-arm queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
   c114af1..f1fcb68  master     -> master
 - [tag update]      patchew/20210115210456.1053477-1-richard.henderson@linaro.org -> patchew/20210115210456.1053477-1-richard.henderson@linaro.org
 - [tag update]      patchew/20210118123448.307825-1-kwolf@redhat.com -> patchew/20210118123448.307825-1-kwolf@redhat.com
 - [tag update]      patchew/20210118163113.780171-1-pbonzini@redhat.com -> patchew/20210118163113.780171-1-pbonzini@redhat.com
 - [tag update]      patchew/20210119144032.305380-1-pbonzini@redhat.com -> patchew/20210119144032.305380-1-pbonzini@redhat.com
 * [new tag]         patchew/20210119151104.16264-1-peter.maydell@linaro.org -> patchew/20210119151104.16264-1-peter.maydell@linaro.org
Switched to a new branch 'test'
aa63d81 docs: Build and install all the docs in a single manual
ff9c40d target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
754cc2b npcm7xx_adc-test: Fix memleak in adc_qom_set
7cd67a0 tests/qtest: add a test case for pvpanic-pci
1661241 pvpanic : update pvpanic spec document
9dadc4f hw/misc/pvpanic: add PCI interface support
6f421bc hw/misc/pvpanic: split-out generic and bus dependent code
c0b7cac target/arm: Update REV, PUNPK for pred_desc
6573b29 target/arm: Update ZIP, UZP, TRN for pred_desc
f4338e1 target/arm: Update PFIRST, PNEXT for pred_desc
34fbd9e target/arm: Introduce PREDDESC field definitions
33a243c target/arm: refactor vae1_tlbmask()
37bbe6b target/arm: enable Secure EL2 in max CPU
9074a0d target/arm: Implement SCR_EL2.EEL2
f5a272b target/arm: revector to run-time pick target EL
ca06afd target/arm: set HPFAR_EL2.NS on secure stage 2 faults
e81a239 target/arm: secure stage 2 translation regime
8063974 target/arm: generalize 2-stage page-walk condition
c2fb95e target/arm: translate NS bit in page-walks
21980ca target/arm: do S1_ptw_translate() before address space lookup
fc3932f target/arm: handle VMID change in secure state
7690e7c target/arm: add ARMv8.4-SEL2 system registers
cb61b29 target/arm: add MMU stage 1 for Secure EL2
6968841 target/arm: add 64-bit S-EL2 to EL exception table
733a019 target/arm: Define isar_feature function to test for presence of SEL2
4e60cf8 target/arm: factor MDCR_EL2 common handling
b5c5cb6 target/arm: use arm_hcr_el2_eff() where applicable
8462601 target/arm: use arm_is_el2_enabled() where applicable
cfd1d61 target/arm: add arm_is_el2_enabled() helper
b2d2a82 target/arm: remove redundant tests
1f43e13 target/arm: Use object_property_add_bool for "sve" property
f6c437b target/arm: Add cpu properties to control pauth
fd151e4 target/arm: Implement an IMPDEF pauth algorithm

=== OUTPUT BEGIN ===
1/33 Checking commit fd151e40ad26 (target/arm: Implement an IMPDEF pauth algorithm)
2/33 Checking commit f6c437b89b8a (target/arm: Add cpu properties to control pauth)
3/33 Checking commit 1f43e13a98da (target/arm: Use object_property_add_bool for "sve" property)
4/33 Checking commit b2d2a82f259e (target/arm: remove redundant tests)
5/33 Checking commit cfd1d619303f (target/arm: add arm_is_el2_enabled() helper)
6/33 Checking commit 846260135460 (target/arm: use arm_is_el2_enabled() where applicable)
7/33 Checking commit b5c5cb67f89e (target/arm: use arm_hcr_el2_eff() where applicable)
8/33 Checking commit 4e60cf8eff3d (target/arm: factor MDCR_EL2 common handling)
9/33 Checking commit 733a019d02cf (target/arm: Define isar_feature function to test for presence of SEL2)
10/33 Checking commit 696884163395 (target/arm: add 64-bit S-EL2 to EL exception table)
WARNING: Block comments use a leading /* on a separate line
#37: FILE: target/arm/helper.c:9005:
+       {/* 1   0   0   1 */{ 2,  2,  2, -1 },{ 2,  2, -1,  1 },},},

WARNING: Block comments use a leading /* on a separate line
#38: FILE: target/arm/helper.c:9006:
+      {{/* 1   0   1   0 */{ 1,  1,  1, -1 },{ 1,  1,  1,  1 },},

WARNING: Block comments use a leading /* on a separate line
#39: FILE: target/arm/helper.c:9007:
+       {/* 1   0   1   1 */{ 2,  2,  2, -1 },{ 2,  2,  2,  1 },},},},

WARNING: Block comments use a leading /* on a separate line
#44: FILE: target/arm/helper.c:9010:
+      {{/* 1   1   1   0 */{ 3,  3,  3, -1 },{ 3,  3,  3,  3 },},

WARNING: Block comments use a leading /* on a separate line
#45: FILE: target/arm/helper.c:9011:
+       {/* 1   1   1   1 */{ 3,  3,  3, -1 },{ 3,  3,  3,  3 },},},},},

WARNING: Block comments use a leading /* on a separate line
#58: FILE: target/arm/op_helper.c:655:
+        /* Requesting a trap to EL2 when we're in EL3 is

total: 0 errors, 6 warnings, 30 lines checked

Patch 10/33 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/33 Checking commit cb61b29082ea (target/arm: add MMU stage 1 for Secure EL2)
12/33 Checking commit 7690e7c1a05c (target/arm: add ARMv8.4-SEL2 system registers)
13/33 Checking commit fc3932f4b7eb (target/arm: handle VMID change in secure state)
14/33 Checking commit 21980cabcb9b (target/arm: do S1_ptw_translate() before address space lookup)
15/33 Checking commit c2fb95e435d0 (target/arm: translate NS bit in page-walks)
16/33 Checking commit 8063974dff0f (target/arm: generalize 2-stage page-walk condition)
17/33 Checking commit e81a2390c582 (target/arm: secure stage 2 translation regime)
18/33 Checking commit ca06afdd1568 (target/arm: set HPFAR_EL2.NS on secure stage 2 faults)
19/33 Checking commit f5a272bd3d4b (target/arm: revector to run-time pick target EL)
20/33 Checking commit 9074a0dec112 (target/arm: Implement SCR_EL2.EEL2)
WARNING: Block comments use a leading /* on a separate line
#92: FILE: target/arm/helper.c:3397:
+        /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in

total: 0 errors, 1 warnings, 110 lines checked

Patch 20/33 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/33 Checking commit 37bbe6b83f65 (target/arm: enable Secure EL2 in max CPU)
22/33 Checking commit 33a243cd07a3 (target/arm: refactor vae1_tlbmask())
23/33 Checking commit 34fbd9e41fcd (target/arm: Introduce PREDDESC field definitions)
24/33 Checking commit f4338e141e6f (target/arm: Update PFIRST, PNEXT for pred_desc)
25/33 Checking commit 6573b2952a1c (target/arm: Update ZIP, UZP, TRN for pred_desc)
26/33 Checking commit c0b7cac1472c (target/arm: Update REV, PUNPK for pred_desc)
27/33 Checking commit 6f421bc572ca (hw/misc/pvpanic: split-out generic and bus dependent code)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#87: 
new file mode 100644

ERROR: line over 90 characters
#159: FILE: hw/misc/pvpanic-isa.c:68:
+    DEFINE_PROP_UINT8("events", PVPanicISAState, pvpanic.events, PVPANIC_PANICKED | PVPANIC_CRASHLOADED),

WARNING: line over 80 characters
#255: FILE: hw/misc/pvpanic.c:69:
+    memory_region_init_io(&s->mr, OBJECT(dev), &pvpanic_ops, s, "pvpanic", size);

total: 1 errors, 2 warnings, 238 lines checked

Patch 27/33 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

28/33 Checking commit 9dadc4f92098 (hw/misc/pvpanic: add PCI interface support)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#68: 
new file mode 100644

total: 0 errors, 1 warnings, 135 lines checked

Patch 28/33 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
29/33 Checking commit 1661241c2357 (pvpanic : update pvpanic spec document)
30/33 Checking commit 7cd67a0a9d90 (tests/qtest: add a test case for pvpanic-pci)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#33: 
new file mode 100644

total: 0 errors, 1 warnings, 69 lines checked

Patch 30/33 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
31/33 Checking commit 754cc2b92505 (npcm7xx_adc-test: Fix memleak in adc_qom_set)
32/33 Checking commit ff9c40da1e28 (target/arm/m_helper: Silence GCC 10 maybe-uninitialized error)
33/33 Checking commit aa63d810085e (docs: Build and install all the docs in a single manual)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#133: 
deleted file mode 100644

total: 0 errors, 1 warnings, 159 lines checked

Patch 33/33 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20210119151104.16264-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

[PULL 00/33] target-arm queue

[Peter Maydell]

Hi; here's the first target-arm pullreq for the 7.0 cycle.

thanks
-- PMM

The following changes since commit 76b56fdfc9fa43ec6e5986aee33f108c6c6a511e:

  Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2021-12-14 12:46:18 -0800)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211215

for you to fetch changes up to aed176558806674d030a8305d989d4e6a5073359:

  tests/acpi: add expected blob for VIOT test on virt machine (2021-12-15 10:35:26 +0000)

----------------------------------------------------------------
target-arm queue:
 * ITS: error reporting cleanup
 * aspeed: improve documentation
 * Fix STM32F2XX USART data register readout
 * allow emulated GICv3 to be disabled in non-TCG builds
 * fix exception priority for singlestep, misaligned PC, bp, etc
 * Correct calculation of tlb range invalidate length
 * npcm7xx_emc: fix missing queue_flush
 * virt: Add VIOT ACPI table for virtio-iommu
 * target/i386: Use assert() to sanity-check b1 in SSE decode
 * Don't include qemu-common unnecessarily

----------------------------------------------------------------
Alex Bennée (1):
      hw/intc: clean-up error reporting for failed ITS cmd

Jean-Philippe Brucker (8):
      hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu
      hw/arm/virt: Remove device tree restriction for virtio-iommu
      hw/arm/virt: Reject instantiation of multiple IOMMUs
      hw/arm/virt: Use object_property_set instead of qdev_prop_set
      tests/acpi: allow updates of VIOT expected data files
      tests/acpi: add test case for VIOT
      tests/acpi: add expected blobs for VIOT test on q35 machine
      tests/acpi: add expected blob for VIOT test on virt machine

Joel Stanley (4):
      docs: aspeed: Add new boards
      docs: aspeed: Update OpenBMC image URL
      docs: aspeed: Give an example of booting a kernel
      docs: aspeed: ADC is now modelled

Olivier Hériveaux (1):
      Fix STM32F2XX USART data register readout

Patrick Venture (1):
      hw/net: npcm7xx_emc fix missing queue_flush

Peter Maydell (6):
      target/i386: Use assert() to sanity-check b1 in SSE decode
      include/hw/i386: Don't include qemu-common.h in .h files
      target/hexagon/cpu.h: don't include qemu-common.h
      target/rx/cpu.h: Don't include qemu-common.h
      hw/arm: Don't include qemu-common.h unnecessarily
      target/arm: Correct calculation of tlb range invalidate length

Philippe Mathieu-Daudé (2):
      hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from arm_gicv3_cpuif.c
      hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig selector

Richard Henderson (10):
      target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn
      target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn
      target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn
      target/arm: Split arm_pre_translate_insn
      target/arm: Advance pc for arch single-step exception
      target/arm: Split compute_fsr_fsc out of arm_deliver_fault
      target/arm: Take an exception if PC is misaligned
      target/arm: Assert thumb pc is aligned
      target/arm: Suppress bp for exceptions with more priority
      tests/tcg: Add arm and aarch64 pc alignment tests

 docs/system/arm/aspeed.rst        |  26 ++++++++++++----
 include/hw/i386/microvm.h         |   1 -
 include/hw/i386/x86.h             |   1 -
 target/arm/helper.h               |   1 +
 target/arm/syndrome.h             |   5 +++
 target/hexagon/cpu.h              |   1 -
 target/rx/cpu.h                   |   1 -
 hw/arm/boot.c                     |   1 -
 hw/arm/digic_boards.c             |   1 -
 hw/arm/highbank.c                 |   1 -
 hw/arm/npcm7xx_boards.c           |   1 -
 hw/arm/sbsa-ref.c                 |   1 -
 hw/arm/stm32f405_soc.c            |   1 -
 hw/arm/vexpress.c                 |   1 -
 hw/arm/virt-acpi-build.c          |   7 +++++
 hw/arm/virt.c                     |  21 ++++++-------
 hw/char/stm32f2xx_usart.c         |   3 +-
 hw/intc/arm_gicv3.c               |   2 +-
 hw/intc/arm_gicv3_cpuif.c         |  10 +-----
 hw/intc/arm_gicv3_cpuif_common.c  |  22 +++++++++++++
 hw/intc/arm_gicv3_its.c           |  39 +++++++++++++++--------
 hw/net/npcm7xx_emc.c              |  18 +++++------
 hw/virtio/virtio-iommu-pci.c      |  12 ++------
 linux-user/aarch64/cpu_loop.c     |  46 ++++++++++++++++------------
 linux-user/hexagon/cpu_loop.c     |   1 +
 target/arm/debug_helper.c         |  23 ++++++++++++++
 target/arm/gdbstub.c              |   9 ++++--
 target/arm/helper.c               |   6 ++--
 target/arm/machine.c              |  10 ++++++
 target/arm/tlb_helper.c           |  63 ++++++++++++++++++++++++++++----------
 target/arm/translate-a64.c        |  23 ++++++++++++--
 target/arm/translate.c            |  58 ++++++++++++++++++++++++++---------
 target/i386/tcg/translate.c       |  12 ++------
 tests/qtest/bios-tables-test.c    |  38 +++++++++++++++++++++++
 tests/tcg/aarch64/pcalign-a64.c   |  37 ++++++++++++++++++++++
 tests/tcg/arm/pcalign-a32.c       |  46 ++++++++++++++++++++++++++++
 hw/arm/Kconfig                    |   1 +
 hw/intc/Kconfig                   |   5 +++
 hw/intc/meson.build               |  11 ++++---
 tests/data/acpi/q35/DSDT.viot     | Bin 0 -> 9398 bytes
 tests/data/acpi/q35/VIOT.viot     | Bin 0 -> 112 bytes
 tests/data/acpi/virt/VIOT         | Bin 0 -> 88 bytes
 tests/tcg/aarch64/Makefile.target |   4 +--
 tests/tcg/arm/Makefile.target     |   4 +++
 44 files changed, 429 insertions(+), 145 deletions(-)
 create mode 100644 hw/intc/arm_gicv3_cpuif_common.c
 create mode 100644 tests/tcg/aarch64/pcalign-a64.c
 create mode 100644 tests/tcg/arm/pcalign-a32.c
 create mode 100644 tests/data/acpi/q35/DSDT.viot
 create mode 100644 tests/data/acpi/q35/VIOT.viot
 create mode 100644 tests/data/acpi/virt/VIOT

[PULL 01/33] hw/intc: clean-up error reporting for failed ITS cmd

[Peter Maydell]

From: Alex Bennée <alex.bennee@linaro.org>

While trying to debug a GIC ITS failure I saw some guest errors that
had poor formatting as well as leaving me confused as to what failed.
As most of the checks aren't possible without a valid dte split that
check apart and then check the other conditions in steps. This avoids
us relying on undefined data.

I still get a failure with the current kvm-unit-tests but at least I
know (partially) why now:

  Exception return from AArch64 EL1 to AArch64 EL1 PC 0x40080588
  PASS: gicv3: its-trigger: inv/invall: dev2/eventid=20 now triggers an LPI
  ITS: MAPD devid=2 size = 0x8 itt=0x40430000 valid=0
  INT dev_id=2 event_id=20
  process_its_cmd: invalid command attributes: invalid dte: 0 for 2 (MEM_TX: 0)
  PASS: gicv3: its-trigger: mapd valid=false: no LPI after device unmap
  SUMMARY: 6 tests, 1 unexpected failures

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20211112170454.3158925-1-alex.bennee@linaro.org
Cc: Shashi Mallela <shashi.mallela@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_its.c | 39 +++++++++++++++++++++++++++------------
 1 file changed, 27 insertions(+), 12 deletions(-)

diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index c929a9cb5c3..b99e63d58f7 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -274,21 +274,36 @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t value, uint32_t offset,
         if (res != MEMTX_OK) {
             return result;
         }
+    } else {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid command attributes: "
+                      "invalid dte: %"PRIx64" for %d (MEM_TX: %d)\n",
+                      __func__, dte, devid, res);
+        return result;
     }
 
-    if ((devid > s->dt.maxids.max_devids) || !dte_valid || !ite_valid ||
-            !cte_valid || (eventid > max_eventid)) {
+
+    /*
+     * In this implementation, in case of guest errors we ignore the
+     * command and move onto the next command in the queue.
+     */
+    if (devid > s->dt.maxids.max_devids) {
         qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: invalid command attributes "
-                      "devid %d or eventid %d or invalid dte %d or"
-                      "invalid cte %d or invalid ite %d\n",
-                      __func__, devid, eventid, dte_valid, cte_valid,
-                      ite_valid);
-        /*
-         * in this implementation, in case of error
-         * we ignore this command and move onto the next
-         * command in the queue
-         */
+                      "%s: invalid command attributes: devid %d>%d",
+                      __func__, devid, s->dt.maxids.max_devids);
+
+    } else if (!dte_valid || !ite_valid || !cte_valid) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid command attributes: "
+                      "dte: %s, ite: %s, cte: %s\n",
+                      __func__,
+                      dte_valid ? "valid" : "invalid",
+                      ite_valid ? "valid" : "invalid",
+                      cte_valid ? "valid" : "invalid");
+    } else if (eventid > max_eventid) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid command attributes: eventid %d > %d\n",
+                      __func__, eventid, max_eventid);
     } else {
         /*
          * Current implementation only supports rdbase == procnum
-- 
2.25.1

[PULL 02/33] docs: aspeed: Add new boards

[Peter Maydell]

From: Joel Stanley <joel@jms.id.au>

Add X11, FP5280G2, G220A, Rainier and Fuji. Mention that Swift will be
removed in v7.0.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20211117065752.330632-2-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/aspeed.rst | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index cec87e3743d..41a9bd5608e 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -14,6 +14,7 @@ AST2400 SoC based machines :
 
 - ``palmetto-bmc``         OpenPOWER Palmetto POWER8 BMC
 - ``quanta-q71l-bmc``      OpenBMC Quanta BMC
+- ``supermicrox11-bmc``    Supermicro X11 BMC
 
 AST2500 SoC based machines :
 
@@ -21,12 +22,16 @@ AST2500 SoC based machines :
 - ``romulus-bmc``          OpenPOWER Romulus POWER9 BMC
 - ``witherspoon-bmc``      OpenPOWER Witherspoon POWER9 BMC
 - ``sonorapass-bmc``       OCP SonoraPass BMC
-- ``swift-bmc``            OpenPOWER Swift BMC POWER9
+- ``swift-bmc``            OpenPOWER Swift BMC POWER9 (to be removed in v7.0)
+- ``fp5280g2-bmc``         Inspur FP5280G2 BMC
+- ``g220a-bmc``            Bytedance G220A BMC
 
 AST2600 SoC based machines :
 
 - ``ast2600-evb``          Aspeed AST2600 Evaluation board (Cortex-A7)
 - ``tacoma-bmc``           OpenPOWER Witherspoon POWER9 AST2600 BMC
+- ``rainier-bmc``          IBM Rainier POWER10 BMC
+- ``fuji-bmc``             Facebook Fuji BMC
 
 Supported devices
 -----------------
-- 
2.25.1

[PULL 03/33] docs: aspeed: Update OpenBMC image URL

[Peter Maydell]

From: Joel Stanley <joel@jms.id.au>

This is the latest URL for the OpenBMC CI. The old URL still works, but
redirects.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-id: 20211117065752.330632-3-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/aspeed.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 41a9bd5608e..b87697fcf0b 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -82,7 +82,7 @@ The Aspeed machines can be started using the ``-kernel`` option to
 load a Linux kernel or from a firmware. Images can be downloaded from
 the OpenBMC jenkins :
 
-   https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/distro=ubuntu,label=docker-builder
+   https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/
 
 or directly from the OpenBMC GitHub release repository :
 
-- 
2.25.1

[PULL 04/33] docs: aspeed: Give an example of booting a kernel

[Peter Maydell]

From: Joel Stanley <joel@jms.id.au>

A common use case for the ASPEED machine is to boot a Linux kernel.
Provide a full example command line.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-id: 20211117065752.330632-4-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/aspeed.rst | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index b87697fcf0b..6aafd611e9a 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -78,9 +78,9 @@ Missing devices
 Boot options
 ------------
 
-The Aspeed machines can be started using the ``-kernel`` option to
-load a Linux kernel or from a firmware. Images can be downloaded from
-the OpenBMC jenkins :
+The Aspeed machines can be started using the ``-kernel`` and ``-dtb`` options
+to load a Linux kernel or from a firmware. Images can be downloaded from the
+OpenBMC jenkins :
 
    https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/
 
@@ -88,6 +88,15 @@ or directly from the OpenBMC GitHub release repository :
 
    https://github.com/openbmc/openbmc/releases
 
+To boot a kernel directly from a Linux build tree:
+
+.. code-block:: bash
+
+  $ qemu-system-arm -M ast2600-evb -nographic \
+        -kernel arch/arm/boot/zImage \
+        -dtb arch/arm/boot/dts/aspeed-ast2600-evb.dtb \
+        -initrd rootfs.cpio
+
 The image should be attached as an MTD drive. Run :
 
 .. code-block:: bash
-- 
2.25.1

[PULL 05/33] docs: aspeed: ADC is now modelled

[Peter Maydell]

From: Joel Stanley <joel@jms.id.au>

Move it to the supported list.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-id: 20211117065752.330632-5-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/aspeed.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 6aafd611e9a..d8b102fa0ad 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -56,13 +56,13 @@ Supported devices
  * Front LEDs (PCA9552 on I2C bus)
  * LPC Peripheral Controller (a subset of subdevices are supported)
  * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA
+ * ADC
 
 
 Missing devices
 ---------------
 
  * Coprocessor support
- * ADC (out of tree implementation)
  * PWM and Fan Controller
  * Slave GPIO Controller
  * Super I/O Controller
-- 
2.25.1

[PULL 06/33] Fix STM32F2XX USART data register readout

[Peter Maydell]

From: Olivier Hériveaux <olivier.heriveaux@ledger.fr>

Fix issue where the data register may be overwritten by next character
reception before being read and returned.

Signed-off-by: Olivier Hériveaux <olivier.heriveaux@ledger.fr>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211128120723.4053-1-olivier.heriveaux@ledger.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/stm32f2xx_usart.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
index 8df0832424c..fde67f4f03f 100644
--- a/hw/char/stm32f2xx_usart.c
+++ b/hw/char/stm32f2xx_usart.c
@@ -103,10 +103,11 @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
         return retvalue;
     case USART_DR:
         DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
+        retvalue = s->usart_dr & 0x3FF;
         s->usart_sr &= ~USART_SR_RXNE;
         qemu_chr_fe_accept_input(&s->chr);
         qemu_set_irq(s->irq, 0);
-        return s->usart_dr & 0x3FF;
+        return retvalue;
     case USART_BRR:
         return s->usart_brr;
     case USART_CR1:
-- 
2.25.1

[PULL 07/33] hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from arm_gicv3_cpuif.c

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@redhat.com>

gicv3_set_gicv3state() is used by arm_gicv3_common.c in
arm_gicv3_common_realize(). Since we want to restrict
arm_gicv3_cpuif.c to TCG, extract gicv3_set_gicv3state()
to a new file. Add this file to the meson 'specific'
source set, since it needs access to "cpu.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20211115223619.2599282-2-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_cpuif.c        | 10 +---------
 hw/intc/arm_gicv3_cpuif_common.c | 22 ++++++++++++++++++++++
 hw/intc/meson.build              |  1 +
 3 files changed, 24 insertions(+), 9 deletions(-)
 create mode 100644 hw/intc/arm_gicv3_cpuif_common.c

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 85fc369e550..d7e03d0cab8 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -1,5 +1,5 @@
 /*
- * ARM Generic Interrupt Controller v3
+ * ARM Generic Interrupt Controller v3 (emulation)
  *
  * Copyright (c) 2016 Linaro Limited
  * Written by Peter Maydell
@@ -21,14 +21,6 @@
 #include "hw/irq.h"
 #include "cpu.h"
 
-void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
-{
-    ARMCPU *arm_cpu = ARM_CPU(cpu);
-    CPUARMState *env = &arm_cpu->env;
-
-    env->gicv3state = (void *)s;
-};
-
 static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
 {
     return env->gicv3state;
diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_common.c
new file mode 100644
index 00000000000..ff1239f65db
--- /dev/null
+++ b/hw/intc/arm_gicv3_cpuif_common.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * ARM Generic Interrupt Controller v3
+ *
+ * Copyright (c) 2016 Linaro Limited
+ * Written by Peter Maydell
+ *
+ * This code is licensed under the GPL, version 2 or (at your option)
+ * any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "gicv3_internal.h"
+#include "cpu.h"
+
+void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
+{
+    ARMCPU *arm_cpu = ARM_CPU(cpu);
+    CPUARMState *env = &arm_cpu->env;
+
+    env->gicv3state = (void *)s;
+};
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index c89d2ca180e..11352806db2 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -25,6 +25,7 @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in
 
 specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c'))
 specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c'))
+specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c'))
 specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c'))
 specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))
 specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
-- 
2.25.1

[PULL 08/33] hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig selector

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@redhat.com>

The TYPE_ARM_GICV3 device is an emulated one.  When using
KVM, it is recommended to use the TYPE_KVM_ARM_GICV3 device
(which uses in-kernel support).

When using --with-devices-FOO, it is possible to build a
binary with a specific set of devices. When this binary is
restricted to KVM accelerator, the TYPE_ARM_GICV3 device is
irrelevant, and it is desirable to remove it from the binary.

Therefore introduce the CONFIG_ARM_GIC_TCG Kconfig selector
which select the files required to have the TYPE_ARM_GICV3
device, but also allowing to de-select this device.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20211115223619.2599282-3-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3.c |  2 +-
 hw/intc/Kconfig     |  5 +++++
 hw/intc/meson.build | 10 ++++++----
 3 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
index 9f5f815db9b..715df5421dd 100644
--- a/hw/intc/arm_gicv3.c
+++ b/hw/intc/arm_gicv3.c
@@ -1,5 +1,5 @@
 /*
- * ARM Generic Interrupt Controller v3
+ * ARM Generic Interrupt Controller v3 (emulation)
  *
  * Copyright (c) 2015 Huawei.
  * Copyright (c) 2016 Linaro Limited
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 78aed93c454..010ded7eae0 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -25,6 +25,11 @@ config APIC
     select MSI_NONBROKEN
     select I8259
 
+config ARM_GIC_TCG
+    bool
+    default y
+    depends on ARM_GIC && TCG
+
 config ARM_GIC_KVM
     bool
     default y
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 11352806db2..70080bc161c 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -3,12 +3,14 @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files(
   'arm_gic.c',
   'arm_gic_common.c',
   'arm_gicv2m.c',
-  'arm_gicv3.c',
   'arm_gicv3_common.c',
-  'arm_gicv3_dist.c',
   'arm_gicv3_its_common.c',
-  'arm_gicv3_redist.c',
+))
+softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files(
+  'arm_gicv3.c',
+  'arm_gicv3_dist.c',
   'arm_gicv3_its.c',
+  'arm_gicv3_redist.c',
 ))
 softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c'))
 softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c'))
@@ -26,7 +28,7 @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in
 specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c'))
 specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c'))
 specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c'))
-specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c'))
+specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpuif.c'))
 specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))
 specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
 specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
-- 
2.25.1

[PULL 09/33] target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn

[Peter Maydell]

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index cec672f2296..9c4258ccac2 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14750,6 +14750,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *s = container_of(dcbase, DisasContext, base);
     CPUARMState *env = cpu->env_ptr;
+    uint64_t pc = s->base.pc_next;
     uint32_t insn;
 
     if (s->ss_active && !s->pstate_ss) {
@@ -14769,10 +14770,10 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
         return;
     }
 
-    s->pc_curr = s->base.pc_next;
-    insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b);
+    s->pc_curr = pc;
+    insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b);
     s->insn = insn;
-    s->base.pc_next += 4;
+    s->base.pc_next = pc + 4;
 
     s->fp_access_checked = false;
     s->sve_access_checked = false;
-- 
2.25.1

[PULL 10/33] target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn

[Peter Maydell]

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 98f59259284..c721b2ce42c 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9548,17 +9548,18 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *dc = container_of(dcbase, DisasContext, base);
     CPUARMState *env = cpu->env_ptr;
+    uint32_t pc = dc->base.pc_next;
     unsigned int insn;
 
     if (arm_pre_translate_insn(dc)) {
-        dc->base.pc_next += 4;
+        dc->base.pc_next = pc + 4;
         return;
     }
 
-    dc->pc_curr = dc->base.pc_next;
-    insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
+    dc->pc_curr = pc;
+    insn = arm_ldl_code(env, &dc->base, pc, dc->sctlr_b);
     dc->insn = insn;
-    dc->base.pc_next += 4;
+    dc->base.pc_next = pc + 4;
     disas_arm_insn(dc, insn);
 
     arm_post_translate_insn(dc);
-- 
2.25.1

[PULL 11/33] target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn

[Peter Maydell]

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index c721b2ce42c..1c2a7274dfc 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9618,25 +9618,25 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *dc = container_of(dcbase, DisasContext, base);
     CPUARMState *env = cpu->env_ptr;
+    uint32_t pc = dc->base.pc_next;
     uint32_t insn;
     bool is_16bit;
 
     if (arm_pre_translate_insn(dc)) {
-        dc->base.pc_next += 2;
+        dc->base.pc_next = pc + 2;
         return;
     }
 
-    dc->pc_curr = dc->base.pc_next;
-    insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
+    dc->pc_curr = pc;
+    insn = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b);
     is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
-    dc->base.pc_next += 2;
+    pc += 2;
     if (!is_16bit) {
-        uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next,
-                                       dc->sctlr_b);
-
+        uint32_t insn2 = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b);
         insn = insn << 16 | insn2;
-        dc->base.pc_next += 2;
+        pc += 2;
     }
+    dc->base.pc_next = pc;
     dc->insn = insn;
 
     if (dc->pstate_il) {
-- 
2.25.1

[PULL 12/33] target/arm: Split arm_pre_translate_insn

[Peter Maydell]

From: Richard Henderson <richard.henderson@linaro.org>

Create arm_check_ss_active and arm_check_kernelpage.

Reverse the order of the tests.  While it doesn't matter in practice,
because only user-only has a kernel page and user-only never sets
ss_active, ss_active has priority over execution exceptions and it
is best to keep them in the proper order.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 1c2a7274dfc..0103c75a274 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9502,7 +9502,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
     dc->insn_start = tcg_last_op();
 }
 
-static bool arm_pre_translate_insn(DisasContext *dc)
+static bool arm_check_kernelpage(DisasContext *dc)
 {
 #ifdef CONFIG_USER_ONLY
     /* Intercept jump to the magic kernel page.  */
@@ -9514,7 +9514,11 @@ static bool arm_pre_translate_insn(DisasContext *dc)
         return true;
     }
 #endif
+    return false;
+}
 
+static bool arm_check_ss_active(DisasContext *dc)
+{
     if (dc->ss_active && !dc->pstate_ss) {
         /* Singlestep state is Active-pending.
          * If we're in this state at the start of a TB then either
@@ -9551,7 +9555,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     uint32_t pc = dc->base.pc_next;
     unsigned int insn;
 
-    if (arm_pre_translate_insn(dc)) {
+    if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
         dc->base.pc_next = pc + 4;
         return;
     }
@@ -9622,7 +9626,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     uint32_t insn;
     bool is_16bit;
 
-    if (arm_pre_translate_insn(dc)) {
+    if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
         dc->base.pc_next = pc + 2;
         return;
     }
-- 
2.25.1

[PULL 13/33] target/arm: Advance pc for arch single-step exception

[Peter Maydell]

From: Richard Henderson <richard.henderson@linaro.org>

The size of the code covered by a TranslationBlock cannot be 0;
this is checked via assert in tb_gen_code.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 9c4258ccac2..2986fe13935 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14767,6 +14767,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
         assert(s->base.num_insns == 1);
         gen_swstep_exception(s, 0, 0);
         s->base.is_jmp = DISAS_NORETURN;
+        s->base.pc_next = pc + 4;
         return;
     }
 
-- 
2.25.1

[PULL 14/33] target/arm: Split compute_fsr_fsc out of arm_deliver_fault

[Peter Maydell]

From: Richard Henderson <richard.henderson@linaro.org>

We will reuse this section of arm_deliver_fault for
raising pc alignment faults.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tlb_helper.c | 45 +++++++++++++++++++++++++----------------
 1 file changed, 28 insertions(+), 17 deletions(-)

diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index 12a934e9248..4cacb9658fb 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -49,25 +49,11 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
     return syn;
 }
 
-static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
-                                            MMUAccessType access_type,
-                                            int mmu_idx, ARMMMUFaultInfo *fi)
+static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi,
+                                int target_el, int mmu_idx, uint32_t *ret_fsc)
 {
-    CPUARMState *env = &cpu->env;
-    int target_el;
-    bool same_el;
-    uint32_t syn, exc, fsr, fsc;
     ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
-
-    target_el = exception_target_el(env);
-    if (fi->stage2) {
-        target_el = 2;
-        env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
-        if (arm_is_secure_below_el3(env) && fi->s1ns) {
-            env->cp15.hpfar_el2 |= HPFAR_NS;
-        }
-    }
-    same_el = (arm_current_el(env) == target_el);
+    uint32_t fsr, fsc;
 
     if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
         arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
@@ -88,6 +74,31 @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
         fsc = 0x3f;
     }
 
+    *ret_fsc = fsc;
+    return fsr;
+}
+
+static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
+                                            MMUAccessType access_type,
+                                            int mmu_idx, ARMMMUFaultInfo *fi)
+{
+    CPUARMState *env = &cpu->env;
+    int target_el;
+    bool same_el;
+    uint32_t syn, exc, fsr, fsc;
+
+    target_el = exception_target_el(env);
+    if (fi->stage2) {
+        target_el = 2;
+        env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
+        if (arm_is_secure_below_el3(env) && fi->s1ns) {
+            env->cp15.hpfar_el2 |= HPFAR_NS;
+        }
+    }
+    same_el = (arm_current_el(env) == target_el);
+
+    fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc);
+
     if (access_type == MMU_INST_FETCH) {
         syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);
         exc = EXCP_PREFETCH_ABORT;
-- 
2.25.1

[PULL 15/33] target/arm: Take an exception if PC is misaligned

[Peter Maydell]

From: Richard Henderson <richard.henderson@linaro.org>

For A64, any input to an indirect branch can cause this.

For A32, many indirect branch paths force the branch to be aligned,
but BXWritePC does not.  This includes the BX instruction but also
other interworking changes to PC.  Prior to v8, this case is UNDEFINED.
With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an
exception or force align the PC.

We choose to raise an exception because we have the infrastructure,
it makes the generated code for gen_bx simpler, and it has the
possibility of catching more guest bugs.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h           |  1 +
 target/arm/syndrome.h         |  5 ++++
 linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++++++---------------
 target/arm/tlb_helper.c       | 18 ++++++++++++++
 target/arm/translate-a64.c    | 15 ++++++++++++
 target/arm/translate.c        | 22 ++++++++++++++++-
 6 files changed, 87 insertions(+), 20 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index 448a86edfdc..b463d9343bc 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -47,6 +47,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
 DEF_HELPER_2(exception_internal, void, env, i32)
 DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32)
 DEF_HELPER_2(exception_bkpt_insn, void, env, i32)
+DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl)
 DEF_HELPER_1(setend, void, env)
 DEF_HELPER_2(wfi, void, env, i32)
 DEF_HELPER_1(wfe, void, env)
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index f30f4130a27..8cde8e7243a 100644
--- a/target/arm/syndrome.h
+++ b/target/arm/syndrome.h
@@ -282,4 +282,9 @@ static inline uint32_t syn_illegalstate(void)
     return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 }
 
+static inline uint32_t syn_pcalignment(void)
+{
+    return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
+}
+
 #endif /* TARGET_ARM_SYNDROME_H */
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
index 97e0728b679..f9f3473288f 100644
--- a/linux-user/aarch64/cpu_loop.c
+++ b/linux-user/aarch64/cpu_loop.c
@@ -113,27 +113,35 @@ void cpu_loop(CPUARMState *env)
             break;
         case EXCP_PREFETCH_ABORT:
         case EXCP_DATA_ABORT:
-            /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */
             ec = syn_get_ec(env->exception.syndrome);
-            assert(ec == EC_DATAABORT || ec == EC_INSNABORT);
-
-            /* Both EC have the same format for FSC, or close enough. */
-            fsc = extract32(env->exception.syndrome, 0, 6);
-            switch (fsc) {
-            case 0x04 ... 0x07: /* Translation fault, level {0-3} */
-                si_signo = TARGET_SIGSEGV;
-                si_code = TARGET_SEGV_MAPERR;
+            switch (ec) {
+            case EC_DATAABORT:
+            case EC_INSNABORT:
+                /* Both EC have the same format for FSC, or close enough. */
+                fsc = extract32(env->exception.syndrome, 0, 6);
+                switch (fsc) {
+                case 0x04 ... 0x07: /* Translation fault, level {0-3} */
+                    si_signo = TARGET_SIGSEGV;
+                    si_code = TARGET_SEGV_MAPERR;
+                    break;
+                case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
+                case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
+                    si_signo = TARGET_SIGSEGV;
+                    si_code = TARGET_SEGV_ACCERR;
+                    break;
+                case 0x11: /* Synchronous Tag Check Fault */
+                    si_signo = TARGET_SIGSEGV;
+                    si_code = TARGET_SEGV_MTESERR;
+                    break;
+                case 0x21: /* Alignment fault */
+                    si_signo = TARGET_SIGBUS;
+                    si_code = TARGET_BUS_ADRALN;
+                    break;
+                default:
+                    g_assert_not_reached();
+                }
                 break;
-            case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
-            case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
-                si_signo = TARGET_SIGSEGV;
-                si_code = TARGET_SEGV_ACCERR;
-                break;
-            case 0x11: /* Synchronous Tag Check Fault */
-                si_signo = TARGET_SIGSEGV;
-                si_code = TARGET_SEGV_MTESERR;
-                break;
-            case 0x21: /* Alignment fault */
+            case EC_PCALIGNMENT:
                 si_signo = TARGET_SIGBUS;
                 si_code = TARGET_BUS_ADRALN;
                 break;
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index 4cacb9658fb..b79004e0cca 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -9,6 +9,7 @@
 #include "cpu.h"
 #include "internals.h"
 #include "exec/exec-all.h"
+#include "exec/helper-proto.h"
 
 static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
                                             unsigned int target_el,
@@ -134,6 +135,23 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
     arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
 }
 
+void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc)
+{
+    ARMMMUFaultInfo fi = { .type = ARMFault_Alignment };
+    int target_el = exception_target_el(env);
+    int mmu_idx = cpu_mmu_index(env, true);
+    uint32_t fsc;
+
+    env->exception.vaddress = pc;
+
+    /*
+     * Note that the fsc is not applicable to this exception,
+     * since any syndrome is pcalignment not insn_abort.
+     */
+    env->exception.fsr = compute_fsr_fsc(env, &fi, target_el, mmu_idx, &fsc);
+    raise_exception(env, EXCP_PREFETCH_ABORT, syn_pcalignment(), target_el);
+}
+
 #if !defined(CONFIG_USER_ONLY)
 
 /*
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2986fe13935..130a9ff8d54 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14753,6 +14753,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     uint64_t pc = s->base.pc_next;
     uint32_t insn;
 
+    /* Singlestep exceptions have the highest priority. */
     if (s->ss_active && !s->pstate_ss) {
         /* Singlestep state is Active-pending.
          * If we're in this state at the start of a TB then either
@@ -14771,6 +14772,20 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
         return;
     }
 
+    if (pc & 3) {
+        /*
+         * PC alignment fault.  This has priority over the instruction abort
+         * that we would receive from a translation fault via arm_ldl_code.
+         * This should only be possible after an indirect branch, at the
+         * start of the TB.
+         */
+        assert(s->base.num_insns == 1);
+        gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc));
+        s->base.is_jmp = DISAS_NORETURN;
+        s->base.pc_next = QEMU_ALIGN_UP(pc, 4);
+        return;
+    }
+
     s->pc_curr = pc;
     insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b);
     s->insn = insn;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0103c75a274..45917c3a6d2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9555,7 +9555,27 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     uint32_t pc = dc->base.pc_next;
     unsigned int insn;
 
-    if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
+    /* Singlestep exceptions have the highest priority. */
+    if (arm_check_ss_active(dc)) {
+        dc->base.pc_next = pc + 4;
+        return;
+    }
+
+    if (pc & 3) {
+        /*
+         * PC alignment fault.  This has priority over the instruction abort
+         * that we would receive from a translation fault via arm_ldl_code
+         * (or the execution of the kernelpage entrypoint). This should only
+         * be possible after an indirect branch, at the start of the TB.
+         */
+        assert(dc->base.num_insns == 1);
+        gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc));
+        dc->base.is_jmp = DISAS_NORETURN;
+        dc->base.pc_next = QEMU_ALIGN_UP(pc, 4);
+        return;
+    }
+
+    if (arm_check_kernelpage(dc)) {
         dc->base.pc_next = pc + 4;
         return;
     }
-- 
2.25.1

[PULL 16/33] target/arm: Assert thumb pc is aligned

[Peter Maydell]

From: Richard Henderson <richard.henderson@linaro.org>

Misaligned thumb PC is architecturally impossible.
Assert is better than proceeding, in case we've missed
something somewhere.

Expand a comment about aligning the pc in gdbstub.
Fail an incoming migrate if a thumb pc is misaligned.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub.c   |  9 +++++++--
 target/arm/machine.c   | 10 ++++++++++
 target/arm/translate.c |  3 +++
 3 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index 134da0d0ae3..ca1de475116 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -77,8 +77,13 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 
     tmp = ldl_p(mem_buf);
 
-    /* Mask out low bit of PC to workaround gdb bugs.  This will probably
-       cause problems if we ever implement the Jazelle DBX extensions.  */
+    /*
+     * Mask out low bits of PC to workaround gdb bugs.
+     * This avoids an assert in thumb_tr_translate_insn, because it is
+     * architecturally impossible to misalign the pc.
+     * This will probably cause problems if we ever implement the
+     * Jazelle DBX extensions.
+     */
     if (n == 15) {
         tmp &= ~1;
     }
diff --git a/target/arm/machine.c b/target/arm/machine.c
index c74d8c3f4b3..135d2420b5c 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -794,6 +794,16 @@ static int cpu_post_load(void *opaque, int version_id)
             return -1;
         }
     }
+
+    /*
+     * Misaligned thumb pc is architecturally impossible.
+     * We have an assert in thumb_tr_translate_insn to verify this.
+     * Fail an incoming migrate to avoid this assert.
+     */
+    if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
+        return -1;
+    }
+
     if (!kvm_enabled()) {
         pmu_op_finish(&cpu->env);
     }
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 45917c3a6d2..0a3840d227f 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9646,6 +9646,9 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     uint32_t insn;
     bool is_16bit;
 
+    /* Misaligned thumb PC is architecturally impossible. */
+    assert((dc->base.pc_next & 1) == 0);
+
     if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
         dc->base.pc_next = pc + 2;
         return;
-- 
2.25.1

[PULL 17/33] target/arm: Suppress bp for exceptions with more priority

[Peter Maydell]

From: Richard Henderson <richard.henderson@linaro.org>

Both single-step and pc alignment faults have priority over
breakpoint exceptions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/debug_helper.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 2983e36dd33..32f3caec238 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -220,6 +220,7 @@ bool arm_debug_check_breakpoint(CPUState *cs)
 {
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
+    target_ulong pc;
     int n;
 
     /*
@@ -231,6 +232,28 @@ bool arm_debug_check_breakpoint(CPUState *cs)
         return false;
     }
 
+    /*
+     * Single-step exceptions have priority over breakpoint exceptions.
+     * If single-step state is active-pending, suppress the bp.
+     */
+    if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) {
+        return false;
+    }
+
+    /*
+     * PC alignment faults have priority over breakpoint exceptions.
+     */
+    pc = is_a64(env) ? env->pc : env->regs[15];
+    if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) {
+        return false;
+    }
+
+    /*
+     * Instruction aborts have priority over breakpoint exceptions.
+     * TODO: We would need to look up the page for PC and verify that
+     * it is present and executable.
+     */
+
     for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
         if (bp_wp_matches(cpu, n, false)) {
             return true;
-- 
2.25.1

[PULL 18/33] tests/tcg: Add arm and aarch64 pc alignment tests

[Peter Maydell]

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/tcg/aarch64/pcalign-a64.c   | 37 +++++++++++++++++++++++++
 tests/tcg/arm/pcalign-a32.c       | 46 +++++++++++++++++++++++++++++++
 tests/tcg/aarch64/Makefile.target |  4 +--
 tests/tcg/arm/Makefile.target     |  4 +++
 4 files changed, 89 insertions(+), 2 deletions(-)
 create mode 100644 tests/tcg/aarch64/pcalign-a64.c
 create mode 100644 tests/tcg/arm/pcalign-a32.c

diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a64.c
new file mode 100644
index 00000000000..6b9277f919f
--- /dev/null
+++ b/tests/tcg/aarch64/pcalign-a64.c
@@ -0,0 +1,37 @@
+/* Test PC misalignment exception */
+
+#include <assert.h>
+#include <signal.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+static void *expected;
+
+static void sigbus(int sig, siginfo_t *info, void *vuc)
+{
+    assert(info->si_code == BUS_ADRALN);
+    assert(info->si_addr == expected);
+    exit(EXIT_SUCCESS);
+}
+
+int main()
+{
+    void *tmp;
+
+    struct sigaction sa = {
+        .sa_sigaction = sigbus,
+        .sa_flags = SA_SIGINFO
+    };
+
+    if (sigaction(SIGBUS, &sa, NULL) < 0) {
+        perror("sigaction");
+        return EXIT_FAILURE;
+    }
+
+    asm volatile("adr %0, 1f + 1\n\t"
+                 "str %0, %1\n\t"
+                 "br  %0\n"
+                 "1:"
+                 : "=&r"(tmp), "=m"(expected));
+    abort();
+}
diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c
new file mode 100644
index 00000000000..3c9c8cc97b1
--- /dev/null
+++ b/tests/tcg/arm/pcalign-a32.c
@@ -0,0 +1,46 @@
+/* Test PC misalignment exception */
+
+#ifdef __thumb__
+#error "This test must be compiled for ARM"
+#endif
+
+#include <assert.h>
+#include <signal.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+static void *expected;
+
+static void sigbus(int sig, siginfo_t *info, void *vuc)
+{
+    assert(info->si_code == BUS_ADRALN);
+    assert(info->si_addr == expected);
+    exit(EXIT_SUCCESS);
+}
+
+int main()
+{
+    void *tmp;
+
+    struct sigaction sa = {
+        .sa_sigaction = sigbus,
+        .sa_flags = SA_SIGINFO
+    };
+
+    if (sigaction(SIGBUS, &sa, NULL) < 0) {
+        perror("sigaction");
+        return EXIT_FAILURE;
+    }
+
+    asm volatile("adr %0, 1f + 2\n\t"
+                 "str %0, %1\n\t"
+                 "bx  %0\n"
+                 "1:"
+                 : "=&r"(tmp), "=m"(expected));
+
+    /*
+     * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns
+     * the address or not.  If so, we can legitimately fall through.
+     */
+    return EXIT_SUCCESS;
+}
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index 2c05c90d170..1d967901bd2 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -8,8 +8,8 @@ VPATH 		+= $(ARM_SRC)
 AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
 VPATH 		+= $(AARCH64_SRC)
 
-# Float-convert Tests
-AARCH64_TESTS=fcvt
+# Base architecture tests
+AARCH64_TESTS=fcvt pcalign-a64
 
 fcvt: LDFLAGS+=-lm
 
diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target
index 5ab59ed6ce1..f509d823d4f 100644
--- a/tests/tcg/arm/Makefile.target
+++ b/tests/tcg/arm/Makefile.target
@@ -29,6 +29,10 @@ run-fcvt: fcvt
 	$(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)")
 	$(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)
 
+# PC alignment test
+ARM_TESTS += pcalign-a32
+pcalign-a32: CFLAGS+=-marm
+
 ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y)
 
 # Semihosting smoke test for linux-user
-- 
2.25.1

[PULL 19/33] target/i386: Use assert() to sanity-check b1 in SSE decode

[Peter Maydell]

In the SSE decode function gen_sse(), we combine a byte
'b' and a value 'b1' which can be [0..3], and switch on them:
   b |= (b1 << 8);
   switch (b) {
   ...
   default:
   unknown_op:
       gen_unknown_opcode(env, s);
       return;
   }

In three cases inside this switch, we were then also checking for
 "if (b1 >= 2) { goto unknown_op; }".
However, this can never happen, because the 'case' values in each place
are 0x0nn or 0x1nn and the switch will have directed the b1 == (2, 3)
cases to the default already.

This check was added in commit c045af25a52e9 in 2010; the added code
was unnecessary then as well, and was apparently intended only to
ensure that we never accidentally ended up indexing off the end
of an sse_op_table with only 2 entries as a result of future bugs
in the decode logic.

Change the checks to assert() instead, and make sure they're always
immediately before the array access they are protecting.

Fixes: Coverity CID 1460207
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/i386/tcg/translate.c | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index e9e14515409..05f9336c9b9 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -3519,9 +3519,6 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
         case 0x171: /* shift xmm, im */
         case 0x172:
         case 0x173:
-            if (b1 >= 2) {
-                goto unknown_op;
-            }
             val = x86_ldub_code(env, s);
             if (is_xmm) {
                 tcg_gen_movi_tl(s->T0, val);
@@ -3540,6 +3537,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                                 offsetof(CPUX86State, mmx_t0.MMX_L(1)));
                 op1_offset = offsetof(CPUX86State,mmx_t0);
             }
+            assert(b1 < 2);
             sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 +
                                        (((modrm >> 3)) & 7)][b1];
             if (!sse_fn_epp) {
@@ -3770,10 +3768,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
             rm = modrm & 7;
             reg = ((modrm >> 3) & 7) | REX_R(s);
             mod = (modrm >> 6) & 3;
-            if (b1 >= 2) {
-                goto unknown_op;
-            }
 
+            assert(b1 < 2);
             sse_fn_epp = sse_op_table6[b].op[b1];
             if (!sse_fn_epp) {
                 goto unknown_op;
@@ -4200,10 +4196,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
             rm = modrm & 7;
             reg = ((modrm >> 3) & 7) | REX_R(s);
             mod = (modrm >> 6) & 3;
-            if (b1 >= 2) {
-                goto unknown_op;
-            }
 
+            assert(b1 < 2);
             sse_fn_eppi = sse_op_table7[b].op[b1];
             if (!sse_fn_eppi) {
                 goto unknown_op;
-- 
2.25.1

[PULL 20/33] include/hw/i386: Don't include qemu-common.h in .h files

[Peter Maydell]

The qemu-common.h header is not supposed to be included from any
other header files, only from .c files (as documented in a comment at
the start of it).

include/hw/i386/x86.h and include/hw/i386/microvm.h break this rule.
In fact, the include is not required at all, so we can just drop it
from both files.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20211129200510.1233037-2-peter.maydell@linaro.org
---
 include/hw/i386/microvm.h | 1 -
 include/hw/i386/x86.h     | 1 -
 2 files changed, 2 deletions(-)

diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h
index 4d9c732d4b2..efcbd926fd4 100644
--- a/include/hw/i386/microvm.h
+++ b/include/hw/i386/microvm.h
@@ -18,7 +18,6 @@
 #ifndef HW_I386_MICROVM_H
 #define HW_I386_MICROVM_H
 
-#include "qemu-common.h"
 #include "exec/hwaddr.h"
 #include "qemu/notify.h"
 
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
index bb1cfb88966..a145a303703 100644
--- a/include/hw/i386/x86.h
+++ b/include/hw/i386/x86.h
@@ -17,7 +17,6 @@
 #ifndef HW_I386_X86_H
 #define HW_I386_X86_H
 
-#include "qemu-common.h"
 #include "exec/hwaddr.h"
 #include "qemu/notify.h"
 
-- 
2.25.1

[PULL 21/33] target/hexagon/cpu.h: don't include qemu-common.h

[Peter Maydell]

The qemu-common.h header is not supposed to be included from any
other header files, only from .c files (as documented in a comment at
the start of it).

Move the include to linux-user/hexagon/cpu_loop.c, which needs it for
the declaration of cpu_exec_step_atomic().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Message-id: 20211129200510.1233037-3-peter.maydell@linaro.org
---
 target/hexagon/cpu.h          | 1 -
 linux-user/hexagon/cpu_loop.c | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index de121d950f2..58a0d3870bb 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -23,7 +23,6 @@ typedef struct CPUHexagonState CPUHexagonState;
 
 #include "fpu/softfloat-types.h"
 
-#include "qemu-common.h"
 #include "exec/cpu-defs.h"
 #include "hex_regs.h"
 #include "mmvec/mmvec.h"
diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c
index 6b24cbaba93..e47f8348d56 100644
--- a/linux-user/hexagon/cpu_loop.c
+++ b/linux-user/hexagon/cpu_loop.c
@@ -19,6 +19,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu-common.h"
 #include "qemu.h"
 #include "user-internals.h"
 #include "cpu_loop-common.h"
-- 
2.25.1

[PULL 22/33] target/rx/cpu.h: Don't include qemu-common.h

[Peter Maydell]

The qemu-common.h header is not supposed to be included from any
other header files, only from .c files (as documented in a comment at
the start of it).

Nothing actually relies on target/rx/cpu.h including it, so we can
just drop the include.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-id: 20211129200510.1233037-4-peter.maydell@linaro.org
---
 target/rx/cpu.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 4ac71aec370..657db84ef0a 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -20,7 +20,6 @@
 #define RX_CPU_H
 
 #include "qemu/bitops.h"
-#include "qemu-common.h"
 #include "hw/registerfields.h"
 #include "cpu-qom.h"
 
-- 
2.25.1

[PULL 23/33] hw/arm: Don't include qemu-common.h unnecessarily

[Peter Maydell]

A lot of C files in hw/arm include qemu-common.h when they don't
need anything from it. Drop the include lines.

omap1.c, pxa2xx.c and strongarm.c retain the include because they
use it for the prototype of qemu_get_timedate().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-id: 20211129200510.1233037-5-peter.maydell@linaro.org
---
 hw/arm/boot.c           | 1 -
 hw/arm/digic_boards.c   | 1 -
 hw/arm/highbank.c       | 1 -
 hw/arm/npcm7xx_boards.c | 1 -
 hw/arm/sbsa-ref.c       | 1 -
 hw/arm/stm32f405_soc.c  | 1 -
 hw/arm/vexpress.c       | 1 -
 hw/arm/virt.c           | 1 -
 8 files changed, 8 deletions(-)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 74ad397b1ff..399f8e837ce 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -8,7 +8,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "qemu-common.h"
 #include "qemu/datadir.h"
 #include "qemu/error-report.h"
 #include "qapi/error.h"
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index b771a3d8b74..4093af09cb2 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
@@ -25,7 +25,6 @@
 
 #include "qemu/osdep.h"
 #include "qapi/error.h"
-#include "qemu-common.h"
 #include "qemu/datadir.h"
 #include "hw/boards.h"
 #include "qemu/error-report.h"
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index c3cb315dbc6..4210894d814 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -18,7 +18,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "qemu-common.h"
 #include "qemu/datadir.h"
 #include "qapi/error.h"
 #include "hw/sysbus.h"
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index dec7d16ae51..aff8c870420 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -24,7 +24,6 @@
 #include "hw/qdev-core.h"
 #include "hw/qdev-properties.h"
 #include "qapi/error.h"
-#include "qemu-common.h"
 #include "qemu/datadir.h"
 #include "qemu/units.h"
 #include "sysemu/blockdev.h"
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 358714bd3e8..dd944553f78 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -18,7 +18,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "qemu-common.h"
 #include "qemu/datadir.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
index 0019b7f4785..c07947d9f8b 100644
--- a/hw/arm/stm32f405_soc.c
+++ b/hw/arm/stm32f405_soc.c
@@ -24,7 +24,6 @@
 
 #include "qemu/osdep.h"
 #include "qapi/error.h"
-#include "qemu-common.h"
 #include "exec/address-spaces.h"
 #include "sysemu/sysemu.h"
 #include "hw/arm/stm32f405_soc.h"
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 58481c07629..3e6d63c7f96 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -23,7 +23,6 @@
 
 #include "qemu/osdep.h"
 #include "qapi/error.h"
-#include "qemu-common.h"
 #include "qemu/datadir.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 30da05dfe04..3e2144e31af 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -29,7 +29,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "qemu-common.h"
 #include "qemu/datadir.h"
 #include "qemu/units.h"
 #include "qemu/option.h"
-- 
2.25.1

[PULL 24/33] target/arm: Correct calculation of tlb range invalidate length

[Peter Maydell]

The calculation of the length of TLB range invalidate operations
in tlbi_aa64_range_get_length() is incorrect in two ways:
 * the NUM field is 5 bits, but we read only 4 bits
 * we miscalculate the page_shift value, because of an
   off-by-one error:
    TG 0b00 is invalid
    TG 0b01 is 4K granule size == 4096 == 2^12
    TG 0b10 is 16K granule size == 16384 == 2^14
    TG 0b11 is 64K granule size == 65536 == 2^16
   so page_shift should be (TG - 1) * 2 + 12

Thanks to the bug report submitter Cha HyunSoo for identifying
both these errors.

Fixes: 84940ed82552d3c ("target/arm: Add support for FEAT_TLBIRANGE")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/734
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20211130173257.1274194-1-peter.maydell@linaro.org
---
 target/arm/helper.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9b317899a66..db837d53bd9 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4519,18 +4519,18 @@ static uint64_t tlbi_aa64_range_get_length(CPUARMState *env,
     uint64_t exponent;
     uint64_t length;
 
-    num = extract64(value, 39, 4);
+    num = extract64(value, 39, 5);
     scale = extract64(value, 44, 2);
     page_size_granule = extract64(value, 46, 2);
 
-    page_shift = page_size_granule * 2 + 12;
-
     if (page_size_granule == 0) {
         qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n",
                       page_size_granule);
         return 0;
     }
 
+    page_shift = (page_size_granule - 1) * 2 + 12;
+
     exponent = (5 * scale) + 1;
     length = (num + 1) << (exponent + page_shift);
 
-- 
2.25.1

[PULL 25/33] hw/net: npcm7xx_emc fix missing queue_flush

[Peter Maydell]

From: Patrick Venture <venture@google.com>

The rx_active boolean change to true should always trigger a try_read
call that flushes the queue.

Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20211203221002.1719306-1-venture@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/net/npcm7xx_emc.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c
index 7c892f820fb..545b2b74108 100644
--- a/hw/net/npcm7xx_emc.c
+++ b/hw/net/npcm7xx_emc.c
@@ -284,6 +284,12 @@ static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag)
     emc_set_mista(emc, mista_flag);
 }
 
+static void emc_enable_rx_and_flush(NPCM7xxEMCState *emc)
+{
+    emc->rx_active = true;
+    qemu_flush_queued_packets(qemu_get_queue(emc->nic));
+}
+
 static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc,
                                        const NPCM7xxEMCTxDesc *tx_desc,
                                        uint32_t desc_addr)
@@ -581,13 +587,6 @@ static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t len1)
     return len;
 }
 
-static void emc_try_receive_next_packet(NPCM7xxEMCState *emc)
-{
-    if (emc_can_receive(qemu_get_queue(emc->nic))) {
-        qemu_flush_queued_packets(qemu_get_queue(emc->nic));
-    }
-}
-
 static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned size)
 {
     NPCM7xxEMCState *emc = opaque;
@@ -703,7 +702,7 @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset,
             emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA;
         }
         if (value & REG_MCMDR_RXON) {
-            emc->rx_active = true;
+            emc_enable_rx_and_flush(emc);
         } else {
             emc_halt_rx(emc, 0);
         }
@@ -739,8 +738,7 @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset,
         break;
     case REG_RSDR:
         if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) {
-            emc->rx_active = true;
-            emc_try_receive_next_packet(emc);
+            emc_enable_rx_and_flush(emc);
         }
         break;
     case REG_MIIDA:
-- 
2.25.1

[PULL 26/33] hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu

[Peter Maydell]

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

When a virtio-iommu is instantiated, describe it using the ACPI VIOT
table.

Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-2-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt-acpi-build.c | 7 +++++++
 hw/arm/Kconfig           | 1 +
 2 files changed, 8 insertions(+)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 674f9026525..d0f4867fdfe 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -55,6 +55,7 @@
 #include "kvm_arm.h"
 #include "migration/vmstate.h"
 #include "hw/acpi/ghes.h"
+#include "hw/acpi/viot.h"
 
 #define ARM_SPI_BASE 32
 
@@ -1011,6 +1012,12 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
     }
 #endif
 
+    if (vms->iommu == VIRT_IOMMU_VIRTIO) {
+        acpi_add_table(table_offsets, tables_blob);
+        build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf,
+                   vms->oem_id, vms->oem_table_id);
+    }
+
     /* XSDT is pointed to by RSDP */
     xsdt = tables_blob->len;
     build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id,
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 2d37d29f02b..e6525909438 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -27,6 +27,7 @@ config ARM_VIRT
     select DIMM
     select ACPI_HW_REDUCED
     select ACPI_APEI
+    select ACPI_VIOT
 
 config CHEETAH
     bool
-- 
2.25.1

[PULL 27/33] hw/arm/virt: Remove device tree restriction for virtio-iommu

[Peter Maydell]

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

virtio-iommu is now supported with ACPI VIOT as well as device tree.
Remove the restriction that prevents from instantiating a virtio-iommu
device under ACPI.

Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-3-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c                | 10 ++--------
 hw/virtio/virtio-iommu-pci.c | 12 ++----------
 2 files changed, 4 insertions(+), 18 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 3e2144e31af..e621cada990 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2613,16 +2613,10 @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
     MachineClass *mc = MACHINE_GET_CLASS(machine);
 
     if (device_is_dynamic_sysbus(mc, dev) ||
-       (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) {
+        object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
+        object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
         return HOTPLUG_HANDLER(machine);
     }
-    if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
-        VirtMachineState *vms = VIRT_MACHINE(machine);
-
-        if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) {
-            return HOTPLUG_HANDLER(machine);
-        }
-    }
     return NULL;
 }
 
diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c
index a160ae6b413..6a1df7fe503 100644
--- a/hw/virtio/virtio-iommu-pci.c
+++ b/hw/virtio/virtio-iommu-pci.c
@@ -48,16 +48,8 @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
     VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
 
     if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) {
-        MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
-
-        error_setg(errp,
-                   "%s machine fails to create iommu-map device tree bindings",
-                   mc->name);
-        error_append_hint(errp,
-                          "Check your machine implements a hotplug handler "
-                          "for the virtio-iommu-pci device\n");
-        error_append_hint(errp, "Check the guest is booted without FW or with "
-                          "-no-acpi\n");
+        error_setg(errp, "Check your machine implements a hotplug handler "
+                         "for the virtio-iommu-pci device");
         return;
     }
     for (int i = 0; i < s->nb_reserved_regions; i++) {
-- 
2.25.1

[PULL 28/33] hw/arm/virt: Reject instantiation of multiple IOMMUs

[Peter Maydell]

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

We do not support instantiating multiple IOMMUs. Before adding a
virtio-iommu, check that no other IOMMU is present. This will detect
both "iommu=smmuv3" machine parameter and another virtio-iommu instance.

Fixes: 70e89132c9 ("hw/arm/virt: Add the virtio-iommu device tree mappings")
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-4-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index e621cada990..41c9808a3fd 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2493,6 +2493,11 @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
         hwaddr db_start = 0, db_end = 0;
         char *resv_prop_str;
 
+        if (vms->iommu != VIRT_IOMMU_NONE) {
+            error_setg(errp, "virt machine does not support multiple IOMMUs");
+            return;
+        }
+
         switch (vms->msi_controller) {
         case VIRT_MSI_CTRL_NONE:
             return;
-- 
2.25.1

[PULL 29/33] hw/arm/virt: Use object_property_set instead of qdev_prop_set

[Peter Maydell]

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

To propagate errors to the caller of the pre_plug callback, use the
object_poperty_set*() functions directly instead of the qdev_prop_set*()
helpers.

Suggested-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-5-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 41c9808a3fd..6bce595aba2 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2517,8 +2517,9 @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
                                         db_start, db_end,
                                         VIRTIO_IOMMU_RESV_MEM_T_MSI);
 
-        qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
-        qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
+        object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
+        object_property_set_str(OBJECT(dev), "reserved-regions[0]",
+                                resv_prop_str, errp);
         g_free(resv_prop_str);
     }
 }
-- 
2.25.1

[PULL 30/33] tests/acpi: allow updates of VIOT expected data files

[Peter Maydell]

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

Create empty data files and allow updates for the upcoming VIOT tests.

Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-6-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
 tests/data/acpi/q35/DSDT.viot               | 0
 tests/data/acpi/q35/VIOT.viot               | 0
 tests/data/acpi/virt/VIOT                   | 0
 4 files changed, 3 insertions(+)
 create mode 100644 tests/data/acpi/q35/DSDT.viot
 create mode 100644 tests/data/acpi/q35/VIOT.viot
 create mode 100644 tests/data/acpi/virt/VIOT

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8bf..29b5b1eabc7 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,4 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/virt/VIOT",
+"tests/data/acpi/q35/DSDT.viot",
+"tests/data/acpi/q35/VIOT.viot",
diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT
new file mode 100644
index 00000000000..e69de29bb2d
-- 
2.25.1

[PULL 31/33] tests/acpi: add test case for VIOT

[Peter Maydell]

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

Add two test cases for VIOT, one on the q35 machine and the other on
virt. To test complex topologies the q35 test has two PCIe buses that
bypass the IOMMU (and are therefore not described by VIOT), and two
buses that are translated by virtio-iommu.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-7-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/bios-tables-test.c | 38 ++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 258874167ef..58df53b15b5 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1465,6 +1465,42 @@ static void test_acpi_virt_tcg(void)
     free_test_data(&data);
 }
 
+static void test_acpi_q35_viot(void)
+{
+    test_data data = {
+        .machine = MACHINE_Q35,
+        .variant = ".viot",
+    };
+
+    /*
+     * To keep things interesting, two buses bypass the IOMMU.
+     * VIOT should only describes the other two buses.
+     */
+    test_acpi_one("-machine default_bus_bypass_iommu=on "
+                  "-device virtio-iommu-pci "
+                  "-device pxb-pcie,bus_nr=0x10,id=pcie.100,bus=pcie.0 "
+                  "-device pxb-pcie,bus_nr=0x20,id=pcie.200,bus=pcie.0,bypass_iommu=on "
+                  "-device pxb-pcie,bus_nr=0x30,id=pcie.300,bus=pcie.0",
+                  &data);
+    free_test_data(&data);
+}
+
+static void test_acpi_virt_viot(void)
+{
+    test_data data = {
+        .machine = "virt",
+        .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
+        .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
+        .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
+        .ram_start = 0x40000000ULL,
+        .scan_len = 128ULL * 1024 * 1024,
+    };
+
+    test_acpi_one("-cpu cortex-a57 "
+                  "-device virtio-iommu-pci", &data);
+    free_test_data(&data);
+}
+
 static void test_oem_fields(test_data *data)
 {
     int i;
@@ -1639,6 +1675,7 @@ int main(int argc, char *argv[])
             qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic);
             qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar);
         }
+        qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
     } else if (strcmp(arch, "aarch64") == 0) {
         if (has_tcg) {
             qtest_add_func("acpi/virt", test_acpi_virt_tcg);
@@ -1646,6 +1683,7 @@ int main(int argc, char *argv[])
             qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp);
             qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb);
             qtest_add_func("acpi/virt/oem-fields", test_acpi_oem_fields_virt);
+            qtest_add_func("acpi/virt/viot", test_acpi_virt_viot);
         }
     }
     ret = g_test_run();
-- 
2.25.1

[PULL 32/33] tests/acpi: add expected blobs for VIOT test on q35 machine

[Peter Maydell]

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

Add expected blobs of the VIOT and DSDT table for the VIOT test on the
q35 machine.

Since the test instantiates a virtio device and two PCIe expander
bridges, DSDT.viot has more blocks than the base DSDT.

The VIOT table generated for the q35 test is:

[000h 0000   4]                    Signature : "VIOT"    [Virtual I/O Translation Table]
[004h 0004   4]                 Table Length : 00000070
[008h 0008   1]                     Revision : 00
[009h 0009   1]                     Checksum : 3D
[00Ah 0010   6]                       Oem ID : "BOCHS "
[010h 0016   8]                 Oem Table ID : "BXPC    "
[018h 0024   4]                 Oem Revision : 00000001
[01Ch 0028   4]              Asl Compiler ID : "BXPC"
[020h 0032   4]        Asl Compiler Revision : 00000001

[024h 0036   2]                   Node count : 0003
[026h 0038   2]                  Node offset : 0030
[028h 0040   8]                     Reserved : 0000000000000000

[030h 0048   1]                         Type : 03 [VirtIO-PCI IOMMU]
[031h 0049   1]                     Reserved : 00
[032h 0050   2]                       Length : 0010

[034h 0052   2]                  PCI Segment : 0000
[036h 0054   2]               PCI BDF number : 0010
[038h 0056   8]                     Reserved : 0000000000000000

[040h 0064   1]                         Type : 01 [PCI Range]
[041h 0065   1]                     Reserved : 00
[042h 0066   2]                       Length : 0018

[044h 0068   4]               Endpoint start : 00003000
[048h 0072   2]            PCI Segment start : 0000
[04Ah 0074   2]              PCI Segment end : 0000
[04Ch 0076   2]                PCI BDF start : 3000
[04Eh 0078   2]                  PCI BDF end : 30FF
[050h 0080   2]                  Output node : 0030
[052h 0082   6]                     Reserved : 000000000000

[058h 0088   1]                         Type : 01 [PCI Range]
[059h 0089   1]                     Reserved : 00
[05Ah 0090   2]                       Length : 0018

[05Ch 0092   4]               Endpoint start : 00001000
[060h 0096   2]            PCI Segment start : 0000
[062h 0098   2]              PCI Segment end : 0000
[064h 0100   2]                PCI BDF start : 1000
[066h 0102   2]                  PCI BDF end : 10FF
[068h 0104   2]                  Output node : 0030
[06Ah 0106   6]                     Reserved : 000000000000

And the DSDT diff is:

@@ -5,13 +5,13 @@
  *
  * Disassembling to symbolic ASL+ operators
  *
- * Disassembly of tests/data/acpi/q35/DSDT, Fri Dec 10 15:03:08 2021
+ * Disassembly of /tmp/aml-H9Y5D1, Fri Dec 10 15:02:27 2021
  *
  * Original Table Header:
  *     Signature        "DSDT"
- *     Length           0x00002061 (8289)
+ *     Length           0x000024B6 (9398)
  *     Revision         0x01 **** 32-bit table (V1), no 64-bit math support
- *     Checksum         0xFA
+ *     Checksum         0xA7
  *     OEM ID           "BOCHS "
  *     OEM Table ID     "BXPC    "
  *     OEM Revision     0x00000001 (1)
@@ -3114,6 +3114,339 @@
         }
     }

+    Scope (\_SB)
+    {
+        Device (PC30)
+        {
+            Name (_UID, 0x30)  // _UID: Unique ID
+            Name (_BBN, 0x30)  // _BBN: BIOS Bus Number
+            Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */)  // _HID: Hardware ID
+            Name (_CID, EisaId ("PNP0A03") /* PCI Bus */)  // _CID: Compatible ID
+            Method (_OSC, 4, NotSerialized)  // _OSC: Operating System Capabilities
+            {
+                CreateDWordField (Arg3, Zero, CDW1)
+                If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+                {
+                    CreateDWordField (Arg3, 0x04, CDW2)
+                    CreateDWordField (Arg3, 0x08, CDW3)
+                    Local0 = CDW3 /* \_SB_.PC30._OSC.CDW3 */
+                    Local0 &= 0x1F
+                    If ((Arg1 != One))
+                    {
+                        CDW1 |= 0x08
+                    }
+
+                    If ((CDW3 != Local0))
+                    {
+                        CDW1 |= 0x10
+                    }
+
+                    CDW3 = Local0
+                }
+                Else
+                {
+                    CDW1 |= 0x04
+                }
+
+                Return (Arg3)
+            }
+
+            Method (_PRT, 0, NotSerialized)  // _PRT: PCI Routing Table
+            {
+                Local0 = Package (0x80){}
+                Local1 = Zero
+                While ((Local1 < 0x80))
+                {
+                    Local2 = (Local1 >> 0x02)
+                    Local3 = ((Local1 + Local2) & 0x03)
+                    If ((Local3 == Zero))
+                    {
+                        Local4 = Package (0x04)
+                            {
+                                Zero,
+                                Zero,
+                                LNKD,
+                                Zero
+                            }
+                    }
+
+                    If ((Local3 == One))
+                    {
+                        Local4 = Package (0x04)
+                            {
+                                Zero,
+                                Zero,
+                                LNKA,
+                                Zero
+                            }
+                    }
+
+                    If ((Local3 == 0x02))
+                    {
+                        Local4 = Package (0x04)
+                            {
+                                Zero,
+                                Zero,
+                                LNKB,
+                                Zero
+                            }
+                    }
+
+                    If ((Local3 == 0x03))
+                    {
+                        Local4 = Package (0x04)
+                            {
+                                Zero,
+                                Zero,
+                                LNKC,
+                                Zero
+                            }
+                    }
+
+                    Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
+                    Local4 [One] = (Local1 & 0x03)
+                    Local0 [Local1] = Local4
+                    Local1++
+                }
+
+                Return (Local0)
+            }
+
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+                    0x0000,             // Granularity
+                    0x0030,             // Range Minimum
+                    0x0030,             // Range Maximum
+                    0x0000,             // Translation Offset
+                    0x0001,             // Length
+                    ,, )
+            })
+        }
+    }
+
+    Scope (\_SB)
+    {
+        Device (PC20)
+        {
+            Name (_UID, 0x20)  // _UID: Unique ID
+            Name (_BBN, 0x20)  // _BBN: BIOS Bus Number
+            Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */)  // _HID: Hardware ID
+            Name (_CID, EisaId ("PNP0A03") /* PCI Bus */)  // _CID: Compatible ID
+            Method (_OSC, 4, NotSerialized)  // _OSC: Operating System Capabilities
+            {
+                CreateDWordField (Arg3, Zero, CDW1)
+                If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+                {
+                    CreateDWordField (Arg3, 0x04, CDW2)
+                    CreateDWordField (Arg3, 0x08, CDW3)
+                    Local0 = CDW3 /* \_SB_.PC20._OSC.CDW3 */
+                    Local0 &= 0x1F
+                    If ((Arg1 != One))
+                    {
+                        CDW1 |= 0x08
+                    }
+
+                    If ((CDW3 != Local0))
+                    {
+                        CDW1 |= 0x10
+                    }
+
+                    CDW3 = Local0
+                }
+                Else
+                {
+                    CDW1 |= 0x04
+                }
+
+                Return (Arg3)
+            }
+
+            Method (_PRT, 0, NotSerialized)  // _PRT: PCI Routing Table
+            {
+                Local0 = Package (0x80){}
+                Local1 = Zero
+                While ((Local1 < 0x80))
+                {
+                    Local2 = (Local1 >> 0x02)
+                    Local3 = ((Local1 + Local2) & 0x03)
+                    If ((Local3 == Zero))
+                    {
+                        Local4 = Package (0x04)
+                            {
+                                Zero,
+                                Zero,
+                                LNKD,
+                                Zero
+                            }
+                    }
+
+                    If ((Local3 == One))
+                    {
+                        Local4 = Package (0x04)
+                            {
+                                Zero,
+                                Zero,
+                                LNKA,
+                                Zero
+                            }
+                    }
+
+                    If ((Local3 == 0x02))
+                    {
+                        Local4 = Package (0x04)
+                            {
+                                Zero,
+                                Zero,
+                                LNKB,
+                                Zero
+                            }
+                    }
+
+                    If ((Local3 == 0x03))
+                    {
+                        Local4 = Package (0x04)
+                            {
+                                Zero,
+                                Zero,
+                                LNKC,
+                                Zero
+                            }
+                    }
+
+                    Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
+                    Local4 [One] = (Local1 & 0x03)
+                    Local0 [Local1] = Local4
+                    Local1++
+                }
+
+                Return (Local0)
+            }
+
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+                    0x0000,             // Granularity
+                    0x0020,             // Range Minimum
+                    0x0020,             // Range Maximum
+                    0x0000,             // Translation Offset
+                    0x0001,             // Length
+                    ,, )
+            })
+        }
+    }
+
+    Scope (\_SB)
+    {
+        Device (PC10)
+        {
+            Name (_UID, 0x10)  // _UID: Unique ID
+            Name (_BBN, 0x10)  // _BBN: BIOS Bus Number
+            Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */)  // _HID: Hardware ID
+            Name (_CID, EisaId ("PNP0A03") /* PCI Bus */)  // _CID: Compatible ID
+            Method (_OSC, 4, NotSerialized)  // _OSC: Operating System Capabilities
+            {
+                CreateDWordField (Arg3, Zero, CDW1)
+                If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+                {
+                    CreateDWordField (Arg3, 0x04, CDW2)
+                    CreateDWordField (Arg3, 0x08, CDW3)
+                    Local0 = CDW3 /* \_SB_.PC10._OSC.CDW3 */
+                    Local0 &= 0x1F
+                    If ((Arg1 != One))
+                    {
+                        CDW1 |= 0x08
+                    }
+
+                    If ((CDW3 != Local0))
+                    {
+                        CDW1 |= 0x10
+                    }
+
+                    CDW3 = Local0
+                }
+                Else
+                {
+                    CDW1 |= 0x04
+                }
+
+                Return (Arg3)
+            }
+
+            Method (_PRT, 0, NotSerialized)  // _PRT: PCI Routing Table
+            {
+                Local0 = Package (0x80){}
+                Local1 = Zero
+                While ((Local1 < 0x80))
+                {
+                    Local2 = (Local1 >> 0x02)
+                    Local3 = ((Local1 + Local2) & 0x03)
+                    If ((Local3 == Zero))
+                    {
+                        Local4 = Package (0x04)
+                            {
+                                Zero,
+                                Zero,
+                                LNKD,
+                                Zero
+                            }
+                    }
+
+                    If ((Local3 == One))
+                    {
+                        Local4 = Package (0x04)
+                            {
+                                Zero,
+                                Zero,
+                                LNKA,
+                                Zero
+                            }
+                    }
+
+                    If ((Local3 == 0x02))
+                    {
+                        Local4 = Package (0x04)
+                            {
+                                Zero,
+                                Zero,
+                                LNKB,
+                                Zero
+                            }
+                    }
+
+                    If ((Local3 == 0x03))
+                    {
+                        Local4 = Package (0x04)
+                            {
+                                Zero,
+                                Zero,
+                                LNKC,
+                                Zero
+                            }
+                    }
+
+                    Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
+                    Local4 [One] = (Local1 & 0x03)
+                    Local0 [Local1] = Local4
+                    Local1++
+                }
+
+                Return (Local0)
+            }
+
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+                    0x0000,             // Granularity
+                    0x0010,             // Range Minimum
+                    0x0010,             // Range Maximum
+                    0x0000,             // Translation Offset
+                    0x0001,             // Length
+                    ,, )
+            })
+        }
+    }
+
     Scope (\_SB.PCI0)
     {
         Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
@@ -3121,9 +3454,9 @@
             WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
                 0x0000,             // Granularity
                 0x0000,             // Range Minimum
-                0x00FF,             // Range Maximum
+                0x000F,             // Range Maximum
                 0x0000,             // Translation Offset
-                0x0100,             // Length
+                0x0010,             // Length
                 ,, )
             IO (Decode16,
                 0x0CF8,             // Range Minimum
@@ -3278,6 +3611,26 @@
                 }
             }

+            Device (S10)
+            {
+                Name (_ADR, 0x00020000)  // _ADR: Address
+            }
+
+            Device (S18)
+            {
+                Name (_ADR, 0x00030000)  // _ADR: Address
+            }
+
+            Device (S20)
+            {
+                Name (_ADR, 0x00040000)  // _ADR: Address
+            }
+
+            Device (S28)
+            {
+                Name (_ADR, 0x00050000)  // _ADR: Address
+            }
+
             Method (PCNT, 0, NotSerialized)
             {
             }

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-8-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/bios-tables-test-allowed-diff.h |   2 --
 tests/data/acpi/q35/DSDT.viot               | Bin 0 -> 9398 bytes
 tests/data/acpi/q35/VIOT.viot               | Bin 0 -> 112 bytes
 3 files changed, 2 deletions(-)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 29b5b1eabc7..8367ffe1d40 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,4 +1,2 @@
 /* List of comma-separated changed AML files to ignore */
 "tests/data/acpi/virt/VIOT",
-"tests/data/acpi/q35/DSDT.viot",
-"tests/data/acpi/q35/VIOT.viot",
diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..1c3b4da5cbe81ecab5e1ef50d383b561c5e0f55f 100644
GIT binary patch
literal 9398
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Gu>S+TT-130

literal 0
HcmV?d00001

diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..9b179266ccbf84f1c250ee646812d17e27987764 100644
GIT binary patch
literal 112
zcmWIZ^baXu00LVle`k+i1*eDrX9XZ&1PX!JAex!M0Hgv8m>C3sGzdcgBZCA3T-xBj
Q0Zb)W9Hva*zW_`e0M!8s0RR91

literal 0
HcmV?d00001

-- 
2.25.1

[PULL 33/33] tests/acpi: add expected blob for VIOT test on virt machine

[Peter Maydell]

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

The VIOT blob contains the following:

[000h 0000   4]                    Signature : "VIOT"    [Virtual I/O Translation Table]
[004h 0004   4]                 Table Length : 00000058
[008h 0008   1]                     Revision : 00
[009h 0009   1]                     Checksum : 66
[00Ah 0010   6]                       Oem ID : "BOCHS "
[010h 0016   8]                 Oem Table ID : "BXPC    "
[018h 0024   4]                 Oem Revision : 00000001
[01Ch 0028   4]              Asl Compiler ID : "BXPC"
[020h 0032   4]        Asl Compiler Revision : 00000001

[024h 0036   2]                   Node count : 0002
[026h 0038   2]                  Node offset : 0030
[028h 0040   8]                     Reserved : 0000000000000000

[030h 0048   1]                         Type : 03 [VirtIO-PCI IOMMU]
[031h 0049   1]                     Reserved : 00
[032h 0050   2]                       Length : 0010

[034h 0052   2]                  PCI Segment : 0000
[036h 0054   2]               PCI BDF number : 0008
[038h 0056   8]                     Reserved : 0000000000000000

[040h 0064   1]                         Type : 01 [PCI Range]
[041h 0065   1]                     Reserved : 00
[042h 0066   2]                       Length : 0018

[044h 0068   4]               Endpoint start : 00000000
[048h 0072   2]            PCI Segment start : 0000
[04Ah 0074   2]              PCI Segment end : 0000
[04Ch 0076   2]                PCI BDF start : 0000
[04Eh 0078   2]                  PCI BDF end : 00FF
[050h 0080   2]                  Output node : 0030
[052h 0082   6]                     Reserved : 000000000000

Acked-by: Ani Sinha <ani@anisinha.ca>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-9-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/bios-tables-test-allowed-diff.h |   1 -
 tests/data/acpi/virt/VIOT                   | Bin 0 -> 88 bytes
 2 files changed, 1 deletion(-)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 8367ffe1d40..dfb8523c8bf 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
 /* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/virt/VIOT",
diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..921f40d88c28ba2171a4d664e119914335309e7d 100644
GIT binary patch
literal 88
zcmWIZ^bd((0D?3pe`k+i1*eDrX9XZ&1PX!JAexE60Hgv8m>C3sGzXN&z`)2L0cSHX
I{D-Rq0Q5fy0RR91

literal 0
HcmV?d00001

-- 
2.25.1

Re: [PULL 00/33] target-arm queue

[Richard Henderson]

On 12/15/21 2:40 AM, Peter Maydell wrote:
> Hi; here's the first target-arm pullreq for the 7.0 cycle.
> 
> thanks
> -- PMM
> 
> The following changes since commit 76b56fdfc9fa43ec6e5986aee33f108c6c6a511e:
> 
>    Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2021-12-14 12:46:18 -0800)
> 
> are available in the Git repository at:
> 
>    https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211215
> 
> for you to fetch changes up to aed176558806674d030a8305d989d4e6a5073359:
> 
>    tests/acpi: add expected blob for VIOT test on virt machine (2021-12-15 10:35:26 +0000)
> 
> ----------------------------------------------------------------
> target-arm queue:
>   * ITS: error reporting cleanup
>   * aspeed: improve documentation
>   * Fix STM32F2XX USART data register readout
>   * allow emulated GICv3 to be disabled in non-TCG builds
>   * fix exception priority for singlestep, misaligned PC, bp, etc
>   * Correct calculation of tlb range invalidate length
>   * npcm7xx_emc: fix missing queue_flush
>   * virt: Add VIOT ACPI table for virtio-iommu
>   * target/i386: Use assert() to sanity-check b1 in SSE decode
>   * Don't include qemu-common unnecessarily
> 
> ----------------------------------------------------------------
> Alex Bennée (1):
>        hw/intc: clean-up error reporting for failed ITS cmd
> 
> Jean-Philippe Brucker (8):
>        hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu
>        hw/arm/virt: Remove device tree restriction for virtio-iommu
>        hw/arm/virt: Reject instantiation of multiple IOMMUs
>        hw/arm/virt: Use object_property_set instead of qdev_prop_set
>        tests/acpi: allow updates of VIOT expected data files
>        tests/acpi: add test case for VIOT
>        tests/acpi: add expected blobs for VIOT test on q35 machine
>        tests/acpi: add expected blob for VIOT test on virt machine
> 
> Joel Stanley (4):
>        docs: aspeed: Add new boards
>        docs: aspeed: Update OpenBMC image URL
>        docs: aspeed: Give an example of booting a kernel
>        docs: aspeed: ADC is now modelled
> 
> Olivier Hériveaux (1):
>        Fix STM32F2XX USART data register readout
> 
> Patrick Venture (1):
>        hw/net: npcm7xx_emc fix missing queue_flush
> 
> Peter Maydell (6):
>        target/i386: Use assert() to sanity-check b1 in SSE decode
>        include/hw/i386: Don't include qemu-common.h in .h files
>        target/hexagon/cpu.h: don't include qemu-common.h
>        target/rx/cpu.h: Don't include qemu-common.h
>        hw/arm: Don't include qemu-common.h unnecessarily
>        target/arm: Correct calculation of tlb range invalidate length
> 
> Philippe Mathieu-Daudé (2):
>        hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from arm_gicv3_cpuif.c
>        hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig selector
> 
> Richard Henderson (10):
>        target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn
>        target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn
>        target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn
>        target/arm: Split arm_pre_translate_insn
>        target/arm: Advance pc for arch single-step exception
>        target/arm: Split compute_fsr_fsc out of arm_deliver_fault
>        target/arm: Take an exception if PC is misaligned
>        target/arm: Assert thumb pc is aligned
>        target/arm: Suppress bp for exceptions with more priority
>        tests/tcg: Add arm and aarch64 pc alignment tests
> 
>   docs/system/arm/aspeed.rst        |  26 ++++++++++++----
>   include/hw/i386/microvm.h         |   1 -
>   include/hw/i386/x86.h             |   1 -
>   target/arm/helper.h               |   1 +
>   target/arm/syndrome.h             |   5 +++
>   target/hexagon/cpu.h              |   1 -
>   target/rx/cpu.h                   |   1 -
>   hw/arm/boot.c                     |   1 -
>   hw/arm/digic_boards.c             |   1 -
>   hw/arm/highbank.c                 |   1 -
>   hw/arm/npcm7xx_boards.c           |   1 -
>   hw/arm/sbsa-ref.c                 |   1 -
>   hw/arm/stm32f405_soc.c            |   1 -
>   hw/arm/vexpress.c                 |   1 -
>   hw/arm/virt-acpi-build.c          |   7 +++++
>   hw/arm/virt.c                     |  21 ++++++-------
>   hw/char/stm32f2xx_usart.c         |   3 +-
>   hw/intc/arm_gicv3.c               |   2 +-
>   hw/intc/arm_gicv3_cpuif.c         |  10 +-----
>   hw/intc/arm_gicv3_cpuif_common.c  |  22 +++++++++++++
>   hw/intc/arm_gicv3_its.c           |  39 +++++++++++++++--------
>   hw/net/npcm7xx_emc.c              |  18 +++++------
>   hw/virtio/virtio-iommu-pci.c      |  12 ++------
>   linux-user/aarch64/cpu_loop.c     |  46 ++++++++++++++++------------
>   linux-user/hexagon/cpu_loop.c     |   1 +
>   target/arm/debug_helper.c         |  23 ++++++++++++++
>   target/arm/gdbstub.c              |   9 ++++--
>   target/arm/helper.c               |   6 ++--
>   target/arm/machine.c              |  10 ++++++
>   target/arm/tlb_helper.c           |  63 ++++++++++++++++++++++++++++----------
>   target/arm/translate-a64.c        |  23 ++++++++++++--
>   target/arm/translate.c            |  58 ++++++++++++++++++++++++++---------
>   target/i386/tcg/translate.c       |  12 ++------
>   tests/qtest/bios-tables-test.c    |  38 +++++++++++++++++++++++
>   tests/tcg/aarch64/pcalign-a64.c   |  37 ++++++++++++++++++++++
>   tests/tcg/arm/pcalign-a32.c       |  46 ++++++++++++++++++++++++++++
>   hw/arm/Kconfig                    |   1 +
>   hw/intc/Kconfig                   |   5 +++
>   hw/intc/meson.build               |  11 ++++---
>   tests/data/acpi/q35/DSDT.viot     | Bin 0 -> 9398 bytes
>   tests/data/acpi/q35/VIOT.viot     | Bin 0 -> 112 bytes
>   tests/data/acpi/virt/VIOT         | Bin 0 -> 88 bytes
>   tests/tcg/aarch64/Makefile.target |   4 +--
>   tests/tcg/arm/Makefile.target     |   4 +++
>   44 files changed, 429 insertions(+), 145 deletions(-)
>   create mode 100644 hw/intc/arm_gicv3_cpuif_common.c
>   create mode 100644 tests/tcg/aarch64/pcalign-a64.c
>   create mode 100644 tests/tcg/arm/pcalign-a32.c
>   create mode 100644 tests/data/acpi/q35/DSDT.viot
>   create mode 100644 tests/data/acpi/q35/VIOT.viot
>   create mode 100644 tests/data/acpi/virt/VIOT

Applied, thanks.

r~

Re: [PULL 31/33] tests/acpi: add test case for VIOT

[Richard Henderson]

On 12/15/21 2:40 AM, Peter Maydell wrote:
> From: Jean-Philippe Brucker <jean-philippe@linaro.org>
> 
> Add two test cases for VIOT, one on the q35 machine and the other on
> virt. To test complex topologies the q35 test has two PCIe buses that
> bypass the IOMMU (and are therefore not described by VIOT), and two
> buses that are translated by virtio-iommu.
> 
> Reviewed-by: Eric Auger <eric.auger@redhat.com>
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
> Message-id: 20211210170415.583179-7-jean-philippe@linaro.org
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   tests/qtest/bios-tables-test.c | 38 ++++++++++++++++++++++++++++++++++
>   1 file changed, 38 insertions(+)

I should have been more careful while applying.  The aarch64 host failure for this is not 
transient as I first assumed:

PASS 5 qtest-aarch64/bios-tables-test /aarch64/acpi/virt/oem-fields
qemu-system-aarch64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Invalid argument
Broken pipe
ERROR qtest-aarch64/bios-tables-test - too few tests run (expected 6, got 5)
make: *** [Makefile.mtest:312: run-test-37] Error 1


r~

> 
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> index 258874167ef..58df53b15b5 100644
> --- a/tests/qtest/bios-tables-test.c
> +++ b/tests/qtest/bios-tables-test.c
> @@ -1465,6 +1465,42 @@ static void test_acpi_virt_tcg(void)
>       free_test_data(&data);
>   }
>   
> +static void test_acpi_q35_viot(void)
> +{
> +    test_data data = {
> +        .machine = MACHINE_Q35,
> +        .variant = ".viot",
> +    };
> +
> +    /*
> +     * To keep things interesting, two buses bypass the IOMMU.
> +     * VIOT should only describes the other two buses.
> +     */
> +    test_acpi_one("-machine default_bus_bypass_iommu=on "
> +                  "-device virtio-iommu-pci "
> +                  "-device pxb-pcie,bus_nr=0x10,id=pcie.100,bus=pcie.0 "
> +                  "-device pxb-pcie,bus_nr=0x20,id=pcie.200,bus=pcie.0,bypass_iommu=on "
> +                  "-device pxb-pcie,bus_nr=0x30,id=pcie.300,bus=pcie.0",
> +                  &data);
> +    free_test_data(&data);
> +}
> +
> +static void test_acpi_virt_viot(void)
> +{
> +    test_data data = {
> +        .machine = "virt",
> +        .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
> +        .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
> +        .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
> +        .ram_start = 0x40000000ULL,
> +        .scan_len = 128ULL * 1024 * 1024,
> +    };
> +
> +    test_acpi_one("-cpu cortex-a57 "
> +                  "-device virtio-iommu-pci", &data);
> +    free_test_data(&data);
> +}
> +
>   static void test_oem_fields(test_data *data)
>   {
>       int i;
> @@ -1639,6 +1675,7 @@ int main(int argc, char *argv[])
>               qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic);
>               qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar);
>           }
> +        qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
>       } else if (strcmp(arch, "aarch64") == 0) {
>           if (has_tcg) {
>               qtest_add_func("acpi/virt", test_acpi_virt_tcg);
> @@ -1646,6 +1683,7 @@ int main(int argc, char *argv[])
>               qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp);
>               qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb);
>               qtest_add_func("acpi/virt/oem-fields", test_acpi_oem_fields_virt);
> +            qtest_add_func("acpi/virt/viot", test_acpi_virt_viot);
>           }
>       }
>       ret = g_test_run();
> 

Re: [PULL 31/33] tests/acpi: add test case for VIOT

[Jean-Philippe Brucker]

On Wed, Dec 15, 2021 at 04:59:10PM -0800, Richard Henderson wrote:
> On 12/15/21 2:40 AM, Peter Maydell wrote:
> > From: Jean-Philippe Brucker <jean-philippe@linaro.org>
> > 
> > Add two test cases for VIOT, one on the q35 machine and the other on
> > virt. To test complex topologies the q35 test has two PCIe buses that
> > bypass the IOMMU (and are therefore not described by VIOT), and two
> > buses that are translated by virtio-iommu.
> > 
> > Reviewed-by: Eric Auger <eric.auger@redhat.com>
> > Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> > Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
> > Message-id: 20211210170415.583179-7-jean-philippe@linaro.org
> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > ---
> >   tests/qtest/bios-tables-test.c | 38 ++++++++++++++++++++++++++++++++++
> >   1 file changed, 38 insertions(+)
> 
> I should have been more careful while applying.  The aarch64 host failure
> for this is not transient as I first assumed:
> 
> PASS 5 qtest-aarch64/bios-tables-test /aarch64/acpi/virt/oem-fields
> qemu-system-aarch64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Invalid argument
> Broken pipe
> ERROR qtest-aarch64/bios-tables-test - too few tests run (expected 6, got 5)
> make: *** [Makefile.mtest:312: run-test-37] Error 1

I'm guessing adding "tcg_only = true", like all other virt machine tests
in this file, should work around this, but I don't really understand the
problem because I can't reproduce it on my aarch64 host (I'm running
"configure --target-list=aarch64-softmmu" followed by "make -j10
check-qtest V=1" in a loop)

Does the attached patch fix it for you?

Thanks,
Jean

--- 8< ---
From 6da0e4d98022d173c79e3caab273b226617d5943 Mon Sep 17 00:00:00 2001
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: Thu, 16 Dec 2021 09:15:06 +0000
Subject: [PATCH] tests/qtest/bios-tables-test: Only run VIOT test on TCG

The VIOT test does not always work under KVM on the virt machine:

  PASS 5 qtest-aarch64/bios-tables-test /aarch64/acpi/virt/oem-fields
  qemu-system-aarch64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Invalid argument
  Broken pipe

Make it TCG only.

Reported-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
---
 tests/qtest/bios-tables-test.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 58df53b15b..9a468e29eb 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1489,6 +1489,7 @@ static void test_acpi_virt_viot(void)
 {
     test_data data = {
         .machine = "virt",
+        .tcg_only = true,
         .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
         .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
         .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
-- 
2.34.1

Re: [PULL 31/33] tests/acpi: add test case for VIOT

[Peter Maydell]

On Thu, 16 Dec 2021 at 09:58, Jean-Philippe Brucker
<jean-philippe@linaro.org> wrote:
>
> On Wed, Dec 15, 2021 at 04:59:10PM -0800, Richard Henderson wrote:
> > On 12/15/21 2:40 AM, Peter Maydell wrote:
> > > From: Jean-Philippe Brucker <jean-philippe@linaro.org>
> > >
> > > Add two test cases for VIOT, one on the q35 machine and the other on
> > > virt. To test complex topologies the q35 test has two PCIe buses that
> > > bypass the IOMMU (and are therefore not described by VIOT), and two
> > > buses that are translated by virtio-iommu.
> > >
> > > Reviewed-by: Eric Auger <eric.auger@redhat.com>
> > > Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> > > Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
> > > Message-id: 20211210170415.583179-7-jean-philippe@linaro.org
> > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > > ---
> > >   tests/qtest/bios-tables-test.c | 38 ++++++++++++++++++++++++++++++++++
> > >   1 file changed, 38 insertions(+)
> >
> > I should have been more careful while applying.  The aarch64 host failure
> > for this is not transient as I first assumed:
> >
> > PASS 5 qtest-aarch64/bios-tables-test /aarch64/acpi/virt/oem-fields
> > qemu-system-aarch64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Invalid argument
> > Broken pipe
> > ERROR qtest-aarch64/bios-tables-test - too few tests run (expected 6, got 5)
> > make: *** [Makefile.mtest:312: run-test-37] Error 1
>
> I'm guessing adding "tcg_only = true", like all other virt machine tests
> in this file, should work around this, but I don't really understand the
> problem because I can't reproduce it on my aarch64 host (I'm running
> "configure --target-list=aarch64-softmmu" followed by "make -j10
> check-qtest V=1" in a loop)

What host are you testing on? The test case explicitly asks
for "-cpu cortex-a57", so it is only going to work with KVM
on hosts with a Cortex-A57.

Richard: given I'm off work for Christmas now, if Jean-Philippe's
suggested fix fixes this are you OK with just applying it directly
to un-break the CI ?

thanks
-- PMM

Re: [PULL 31/33] tests/acpi: add test case for VIOT

[Richard Henderson]

On 12/16/21 3:28 AM, Peter Maydell wrote:
> On Thu, 16 Dec 2021 at 09:58, Jean-Philippe Brucker
> <jean-philippe@linaro.org> wrote:
>>
>> On Wed, Dec 15, 2021 at 04:59:10PM -0800, Richard Henderson wrote:
>>> On 12/15/21 2:40 AM, Peter Maydell wrote:
>>>> From: Jean-Philippe Brucker <jean-philippe@linaro.org>
>>>>
>>>> Add two test cases for VIOT, one on the q35 machine and the other on
>>>> virt. To test complex topologies the q35 test has two PCIe buses that
>>>> bypass the IOMMU (and are therefore not described by VIOT), and two
>>>> buses that are translated by virtio-iommu.
>>>>
>>>> Reviewed-by: Eric Auger <eric.auger@redhat.com>
>>>> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
>>>> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
>>>> Message-id: 20211210170415.583179-7-jean-philippe@linaro.org
>>>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>>>> ---
>>>>    tests/qtest/bios-tables-test.c | 38 ++++++++++++++++++++++++++++++++++
>>>>    1 file changed, 38 insertions(+)
>>>
>>> I should have been more careful while applying.  The aarch64 host failure
>>> for this is not transient as I first assumed:
>>>
>>> PASS 5 qtest-aarch64/bios-tables-test /aarch64/acpi/virt/oem-fields
>>> qemu-system-aarch64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Invalid argument
>>> Broken pipe
>>> ERROR qtest-aarch64/bios-tables-test - too few tests run (expected 6, got 5)
>>> make: *** [Makefile.mtest:312: run-test-37] Error 1
>>
>> I'm guessing adding "tcg_only = true", like all other virt machine tests
>> in this file, should work around this, but I don't really understand the
>> problem because I can't reproduce it on my aarch64 host (I'm running
>> "configure --target-list=aarch64-softmmu" followed by "make -j10
>> check-qtest V=1" in a loop)
> 
> What host are you testing on? The test case explicitly asks
> for "-cpu cortex-a57", so it is only going to work with KVM
> on hosts with a Cortex-A57.
> 
> Richard: given I'm off work for Christmas now, if Jean-Philippe's
> suggested fix fixes this are you OK with just applying it directly
> to un-break the CI ?

Yes, it looks like it should fix the problem.  I'll run it through and apply directly.

After the new year we can look to see if -cpu max would not work just as well for most of 
these tests, so that kvm can run them as well.


r~

Re: [PULL 31/33] tests/acpi: add test case for VIOT

[Jean-Philippe Brucker]

On Thu, Dec 16, 2021 at 11:28:04AM +0000, Peter Maydell wrote:
> On Thu, 16 Dec 2021 at 09:58, Jean-Philippe Brucker
> <jean-philippe@linaro.org> wrote:
> >
> > On Wed, Dec 15, 2021 at 04:59:10PM -0800, Richard Henderson wrote:
> > > On 12/15/21 2:40 AM, Peter Maydell wrote:
> > > > From: Jean-Philippe Brucker <jean-philippe@linaro.org>
> > > >
> > > > Add two test cases for VIOT, one on the q35 machine and the other on
> > > > virt. To test complex topologies the q35 test has two PCIe buses that
> > > > bypass the IOMMU (and are therefore not described by VIOT), and two
> > > > buses that are translated by virtio-iommu.
> > > >
> > > > Reviewed-by: Eric Auger <eric.auger@redhat.com>
> > > > Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> > > > Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
> > > > Message-id: 20211210170415.583179-7-jean-philippe@linaro.org
> > > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > > > ---
> > > >   tests/qtest/bios-tables-test.c | 38 ++++++++++++++++++++++++++++++++++
> > > >   1 file changed, 38 insertions(+)
> > >
> > > I should have been more careful while applying.  The aarch64 host failure
> > > for this is not transient as I first assumed:
> > >
> > > PASS 5 qtest-aarch64/bios-tables-test /aarch64/acpi/virt/oem-fields
> > > qemu-system-aarch64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Invalid argument
> > > Broken pipe
> > > ERROR qtest-aarch64/bios-tables-test - too few tests run (expected 6, got 5)
> > > make: *** [Makefile.mtest:312: run-test-37] Error 1
> >
> > I'm guessing adding "tcg_only = true", like all other virt machine tests
> > in this file, should work around this, but I don't really understand the
> > problem because I can't reproduce it on my aarch64 host (I'm running
> > "configure --target-list=aarch64-softmmu" followed by "make -j10
> > check-qtest V=1" in a loop)
> 
> What host are you testing on? The test case explicitly asks
> for "-cpu cortex-a57", so it is only going to work with KVM
> on hosts with a Cortex-A57.

Ah yes that is it, I'm running AMD Seattle which has 8 Cortex-A57. Sorry
about this

Thanks,
Jean

> 
> Richard: given I'm off work for Christmas now, if Jean-Philippe's
> suggested fix fixes this are you OK with just applying it directly
> to un-break the CI ?
> 
> thanks
> -- PMM

[PULL 00/33] target-arm queue

[Peter Maydell]

The following changes since commit bf4460a8d9a86f6cfe05d7a7f470c48e3a93d8b2:

  Merge tag 'pull-tcg-20230123' of https://gitlab.com/rth7680/qemu into staging (2023-02-03 09:30:45 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230203

for you to fetch changes up to bb18151d8bd9bedc497ee9d4e8d81b39a4e5bbf6:

  target/arm: Enable FEAT_FGT on '-cpu max' (2023-02-03 12:59:24 +0000)

----------------------------------------------------------------
target-arm queue:
 * Fix physical address resolution for Stage2
 * pl011: refactoring, implement reset method
 * Support GICv3 with hvf acceleration
 * sbsa-ref: remove cortex-a76 from list of supported cpus
 * Correct syndrome for ATS12NSO* traps at Secure EL1
 * Fix priority of HSTR_EL2 traps vs UNDEFs
 * Implement FEAT_FGT for '-cpu max'

----------------------------------------------------------------
Alexander Graf (3):
      hvf: arm: Add support for GICv3
      hw/arm/virt: Consolidate GIC finalize logic
      hw/arm/virt: Make accels in GIC finalize logic explicit

Evgeny Iakovlev (4):
      hw/char/pl011: refactor FIFO depth handling code
      hw/char/pl011: add post_load hook for backwards-compatibility
      hw/char/pl011: implement a reset method
      hw/char/pl011: better handling of FIFO flags on LCR reset

Marcin Juszkiewicz (1):
      sbsa-ref: remove cortex-a76 from list of supported cpus

Peter Maydell (23):
      target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly
      target/arm: Correct syndrome for ATS12NSO* at Secure EL1
      target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3}
      target/arm: Move do_coproc_insn() syndrome calculation earlier
      target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps
      target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1
      target/arm: Disable HSTR_EL2 traps if EL2 is not enabled
      target/arm: Define the FEAT_FGT registers
      target/arm: Implement FGT trapping infrastructure
      target/arm: Mark up sysregs for HFGRTR bits 0..11
      target/arm: Mark up sysregs for HFGRTR bits 12..23
      target/arm: Mark up sysregs for HFGRTR bits 24..35
      target/arm: Mark up sysregs for HFGRTR bits 36..63
      target/arm: Mark up sysregs for HDFGRTR bits 0..11
      target/arm: Mark up sysregs for HDFGRTR bits 12..63
      target/arm: Mark up sysregs for HFGITR bits 0..11
      target/arm: Mark up sysregs for HFGITR bits 12..17
      target/arm: Mark up sysregs for HFGITR bits 18..47
      target/arm: Mark up sysregs for HFGITR bits 48..63
      target/arm: Implement the HFGITR_EL2.ERET trap
      target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps
      target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps
      target/arm: Enable FEAT_FGT on '-cpu max'

Richard Henderson (2):
      hw/arm: Use TYPE_ARM_SMMUV3
      target/arm: Fix physical address resolution for Stage2

 docs/system/arm/emulation.rst |   1 +
 include/hw/arm/virt.h         |  15 +-
 include/hw/char/pl011.h       |   5 +-
 target/arm/cpregs.h           | 484 +++++++++++++++++++++++++++++++++++++++++-
 target/arm/cpu.h              |  18 ++
 target/arm/internals.h        |  20 ++
 target/arm/syndrome.h         |  10 +
 target/arm/translate.h        |   6 +
 hw/arm/sbsa-ref.c             |   4 +-
 hw/arm/virt.c                 | 203 +++++++++---------
 hw/char/pl011.c               |  93 ++++++--
 hw/intc/arm_gicv3_cpuif.c     |  18 +-
 target/arm/cpu64.c            |   1 +
 target/arm/debug_helper.c     |  46 +++-
 target/arm/helper.c           | 245 ++++++++++++++++++++-
 target/arm/hvf/hvf.c          | 151 +++++++++++++
 target/arm/op_helper.c        |  58 ++++-
 target/arm/ptw.c              |   2 +-
 target/arm/translate-a64.c    |  22 +-
 target/arm/translate.c        | 125 +++++++----
 target/arm/hvf/trace-events   |   2 +
 21 files changed, 1340 insertions(+), 189 deletions(-)

Re: [PULL 00/33] target-arm queue

[Peter Maydell]

On Fri, 3 Feb 2023 at 14:29, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The following changes since commit bf4460a8d9a86f6cfe05d7a7f470c48e3a93d8b2:
>
>   Merge tag 'pull-tcg-20230123' of https://gitlab.com/rth7680/qemu into staging (2023-02-03 09:30:45 +0000)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230203
>
> for you to fetch changes up to bb18151d8bd9bedc497ee9d4e8d81b39a4e5bbf6:
>
>   target/arm: Enable FEAT_FGT on '-cpu max' (2023-02-03 12:59:24 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * Fix physical address resolution for Stage2
>  * pl011: refactoring, implement reset method
>  * Support GICv3 with hvf acceleration
>  * sbsa-ref: remove cortex-a76 from list of supported cpus
>  * Correct syndrome for ATS12NSO* traps at Secure EL1
>  * Fix priority of HSTR_EL2 traps vs UNDEFs
>  * Implement FEAT_FGT for '-cpu max'


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0
for any user-visible changes.

-- PMM

[PULL 00/33] target-arm queue

[Peter Maydell]

Hi; here's a target-arm pullreq. Mostly this is some decodetree
conversion patches from me, plus a scattering of other bug fixes.

thanks
-- PMM

The following changes since commit e3660cc1e3cb136af50c0eaaeac27943c2438d1d:

  Merge tag 'pull-loongarch-20230616' of https://gitlab.com/gaosong/qemu into staging (2023-06-16 12:30:16 +0200)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230619

for you to fetch changes up to 074259c0f2ac40042dce766d870318cc22f388eb:

  hw/misc/bcm2835_property: Handle CORE_CLK_ID firmware property (2023-06-19 15:27:21 +0100)

----------------------------------------------------------------
target-arm queue:
 * Fix return value from LDSMIN/LDSMAX 8/16 bit atomics
 * Return correct result for LDG when ATA=0
 * Conversion of system insns, loads and stores to decodetree
 * hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1
 * hw/sd/allwinner-sdhost: Don't send non-boolean IRQ line levels
 * hw/timer/nrf51_timer: Don't lose time when timer is queried in tight loop
 * hw/arm/Kconfig: sbsa-ref uses Bochs display
 * imx_serial: set wake bit when we receive a data byte
 * docs: sbsa: document board to firmware interface
 * hw/misc/bcm2835_property: avoid hard-coded constants

----------------------------------------------------------------
Marcin Juszkiewicz (2):
      hw/arm/Kconfig: sbsa-ref uses Bochs display
      docs: sbsa: document board to firmware interface

Martin Kaiser (1):
      imx_serial: set wake bit when we receive a data byte

Peter Maydell (26):
      target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics
      target/arm: Return correct result for LDG when ATA=0
      target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode
      target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores
      target/arm: Convert hint instruction space to decodetree
      target/arm: Convert barrier insns to decodetree
      target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree
      target/arm: Convert MSR (immediate) to decodetree
      target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree
      target/arm: Convert exception generation instructions to decodetree
      target/arm: Convert load/store exclusive and ordered to decodetree
      target/arm: Convert LDXP, STXP, CASP, CAS to decodetree
      target/arm: Convert load reg (literal) group to decodetree
      target/arm: Convert load/store-pair to decodetree
      target/arm: Convert ld/st reg+imm9 insns to decodetree
      target/arm: Convert LDR/STR with 12-bit immediate to decodetree
      target/arm: Convert LDR/STR reg+reg to decodetree
      target/arm: Convert atomic memory ops to decodetree
      target/arm: Convert load (pointer auth) insns to decodetree
      target/arm: Convert LDAPR/STLR (imm) to decodetree
      target/arm: Convert load/store (multiple structures) to decodetree
      target/arm: Convert load/store single structure to decodetree
      target/arm: Convert load/store tags insns to decodetree
      hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1
      hw/sd/allwinner-sdhost: Don't send non-boolean IRQ line levels
      hw/timer/nrf51_timer: Don't lose time when timer is queried in tight loop

Sergey Kambalin (4):
      hw/arm/raspi: Import Linux raspi definitions as 'raspberrypi-fw-defs.h'
      hw/misc/bcm2835_property: Use 'raspberrypi-fw-defs.h' definitions
      hw/misc/bcm2835_property: Replace magic frequency values by definitions
      hw/misc/bcm2835_property: Handle CORE_CLK_ID firmware property

 docs/system/arm/sbsa.rst              |   38 +-
 include/hw/arm/raspi_platform.h       |   10 +
 include/hw/char/imx_serial.h          |    1 +
 include/hw/misc/raspberrypi-fw-defs.h |  163 ++
 target/arm/tcg/a64.decode             |  403 ++++
 hw/char/imx_serial.c                  |    5 +-
 hw/intc/allwinner-a10-pic.c           |    2 +-
 hw/misc/bcm2835_property.c            |  112 +-
 hw/sd/allwinner-sdhost.c              |    2 +-
 hw/timer/nrf51_timer.c                |    7 +-
 target/arm/tcg/translate-a64.c        | 3319 +++++++++++++++------------------
 hw/arm/Kconfig                        |    1 +
 12 files changed, 2157 insertions(+), 1906 deletions(-)
 create mode 100644 include/hw/misc/raspberrypi-fw-defs.h

Re: [PULL 00/33] target-arm queue

[Richard Henderson]

On 6/19/23 16:28, Peter Maydell wrote:
> Hi; here's a target-arm pullreq. Mostly this is some decodetree
> conversion patches from me, plus a scattering of other bug fixes.
> 
> thanks
> -- PMM
> 
> The following changes since commit e3660cc1e3cb136af50c0eaaeac27943c2438d1d:
> 
>    Merge tag 'pull-loongarch-20230616' of https://gitlab.com/gaosong/qemu into staging (2023-06-16 12:30:16 +0200)
> 
> are available in the Git repository at:
> 
>    https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230619
> 
> for you to fetch changes up to 074259c0f2ac40042dce766d870318cc22f388eb:
> 
>    hw/misc/bcm2835_property: Handle CORE_CLK_ID firmware property (2023-06-19 15:27:21 +0100)
> 
> ----------------------------------------------------------------
> target-arm queue:
>   * Fix return value from LDSMIN/LDSMAX 8/16 bit atomics
>   * Return correct result for LDG when ATA=0
>   * Conversion of system insns, loads and stores to decodetree
>   * hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1
>   * hw/sd/allwinner-sdhost: Don't send non-boolean IRQ line levels
>   * hw/timer/nrf51_timer: Don't lose time when timer is queried in tight loop
>   * hw/arm/Kconfig: sbsa-ref uses Bochs display
>   * imx_serial: set wake bit when we receive a data byte
>   * docs: sbsa: document board to firmware interface
>   * hw/misc/bcm2835_property: avoid hard-coded constants

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate.


r~

[PULL 00/33] target-arm queue

[Peter Maydell]

Hi; here's the latest target-arm pull request. Nothing too
exciting, just an accumulation of refactorings, minor features
and bugfixes. (I checked that the tag has propagated to all
the git.linaro.org mirrors.)

thanks
-- PMM

The following changes since commit 6c9ae1ce82b65faa3f266fd103729878cf11e07e:

  Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into staging (2023-11-01 06:58:11 +0900)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231102

for you to fetch changes up to 1c98a821a2b3620c516f3da0d74719ed6f33bced:

  tests/qtest: Introduce tests for AMD/Xilinx Versal TRNG device (2023-11-02 14:42:03 +0000)

----------------------------------------------------------------
target-arm queue:
 * linux-user/elfload: Add missing arm64 hwcap values
 * stellaris-gamepad: Convert to qdev
 * docs/specs: Convert various txt docs to rST
 * MAINTAINERS: Make sure that gicv3_internal.h is covered, too
 * hw/arm/pxa2xx_gpio: Pass CPU using QOM link property
 * hw/watchdog/wdt_imx2: Trace MMIO access and timer activity
 * hw/misc/imx7_snvs: Trace MMIO access
 * hw/misc/imx6_ccm: Convert DPRINTF to trace events
 * hw/i2c/pm_smbus: Convert DPRINTF to trace events
 * target/arm: Enable FEAT_MOPS insns in user-mode emulation
 * linux-user: Report AArch64 hwcap2 fields above bit 31
 * target/arm: Make FEAT_MOPS SET* insns handle Xs == XZR correctly
 * target/arm: Fix SVE STR increment
 * hw/char/stm32f2xx_usart: implement TX interrupts
 * target/arm: Correctly propagate stage 1 BTI guarded bit in a two-stage walk
 * xlnx-versal-virt: Add AMD/Xilinx TRNG device

----------------------------------------------------------------
Bernhard Beschow (5):
      hw/watchdog/wdt_imx2: Trace MMIO access
      hw/watchdog/wdt_imx2: Trace timer activity
      hw/misc/imx7_snvs: Trace MMIO access
      hw/misc/imx6_ccm: Convert DPRINTF to trace events
      hw/i2c/pm_smbus: Convert DPRINTF to trace events

Hans-Erik Floryd (3):
      hw/char/stm32f2xx_usart: Extract common IRQ update code to update_irq()
      hw/char/stm32f2xx_usart: Update IRQ when DR is written
      hw/char/stm32f2xx_usart: Add more definitions for CR1 register

Kevin Wolf (1):
      qdev: Add qdev_prop_set_array()

Marielle Novastrider (1):
      linux-user/elfload: Add missing arm64 hwcap values

Peter Maydell (17):
      hw/input/stellaris_input: Rename to stellaris_gamepad
      hw/input/stellaris_gamepad: Rename structs to our usual convention
      hw/input/stellaris_gamepad: Remove StellarisGamepadButton struct
      hw/input/stellaris_input: Convert to qdev
      hw/input/stellaris_gamepad: Convert to qemu_input_handler_register()
      docs/specs/vmw_pvscsi-spec: Convert to rST
      docs/specs/edu: Convert to rST
      docs/specs/ivshmem-spec: Convert to rST
      docs/specs/pvpanic: Convert to rST
      docs/specs/standard-vga: Convert to rST
      docs/specs/virt-ctlr: Convert to rST
      docs/specs/vmcoreinfo: Convert to rST
      docs/specs/vmgenid: Convert to rST
      target/arm: Enable FEAT_MOPS insns in user-mode emulation
      linux-user: Report AArch64 hwcap2 fields above bit 31
      target/arm: Make FEAT_MOPS SET* insns handle Xs == XZR correctly
      target/arm: Correctly propagate stage 1 BTI guarded bit in a two-stage walk

Philippe Mathieu-Daudé (1):
      hw/arm/pxa2xx_gpio: Pass CPU using QOM link property

Richard Henderson (1):
      target/arm: Fix SVE STR increment

Thomas Huth (1):
      MAINTAINERS: Make sure that gicv3_internal.h is covered, too

Tong Ho (3):
      hw/misc: Introduce AMD/Xilix Versal TRNG device
      hw/arm: xlnx-versal-virt: Add AMD/Xilinx TRNG device
      tests/qtest: Introduce tests for AMD/Xilinx Versal TRNG device

 MAINTAINERS                                       |   9 +-
 docs/specs/{edu.txt => edu.rst}                   |  84 ++-
 docs/specs/index.rst                              |   8 +
 docs/specs/{ivshmem-spec.txt => ivshmem-spec.rst} |  63 +-
 docs/specs/pci-ids.rst                            |   2 +-
 docs/specs/{pvpanic.txt => pvpanic.rst}           |  41 +-
 docs/specs/standard-vga.rst                       |  94 +++
 docs/specs/standard-vga.txt                       |  81 ---
 docs/specs/{virt-ctlr.txt => virt-ctlr.rst}       |  12 +-
 docs/specs/vmcoreinfo.rst                         |  54 ++
 docs/specs/vmcoreinfo.txt                         |  53 --
 docs/specs/vmgenid.rst                            | 246 ++++++++
 docs/specs/vmgenid.txt                            | 245 --------
 docs/specs/vmw_pvscsi-spec.rst                    | 115 ++++
 docs/specs/vmw_pvscsi-spec.txt                    |  92 ---
 docs/system/devices/ivshmem.rst                   |   2 +-
 include/hw/arm/xlnx-versal.h                      |   5 +
 include/hw/char/stm32f2xx_usart.h                 |  10 +-
 include/hw/input/gamepad.h                        |  18 -
 include/hw/input/stellaris_gamepad.h              |  37 ++
 include/hw/misc/xlnx-versal-trng.h                |  58 ++
 include/hw/qdev-properties.h                      |   3 +
 linux-user/loader.h                               |   2 +-
 target/arm/cpu-features.h                         |   5 +
 target/arm/internals.h                            |   1 -
 hw/arm/pxa2xx_gpio.c                              |   8 +-
 hw/arm/stellaris.c                                |  34 +-
 hw/arm/xlnx-versal.c                              |  16 +
 hw/char/stm32f2xx_usart.c                         |  29 +-
 hw/core/qdev-properties.c                         |  21 +
 hw/display/vga-isa.c                              |   2 +-
 hw/display/vga-pci.c                              |   2 +-
 hw/i2c/pm_smbus.c                                 |  18 +-
 hw/input/stellaris_gamepad.c                      |  99 +++
 hw/input/stellaris_input.c                        |  93 ---
 hw/misc/imx6_ccm.c                                |  41 +-
 hw/misc/imx7_snvs.c                               |   5 +
 hw/misc/xlnx-versal-trng.c                        | 717 ++++++++++++++++++++++
 hw/watchdog/wdt_imx2.c                            |  28 +-
 linux-user/elfload.c                              |  11 +-
 target/arm/cpu.c                                  |   2 +
 target/arm/ptw.c                                  |   7 +-
 target/arm/tcg/helper-a64.c                       |  15 +-
 target/arm/tcg/translate-sve.c                    |   5 +-
 tests/qtest/xlnx-versal-trng-test.c               | 485 +++++++++++++++
 tests/tcg/aarch64/sve-str.c                       |  49 ++
 hw/arm/Kconfig                                    |   3 +-
 hw/i2c/trace-events                               |   6 +
 hw/input/Kconfig                                  |   2 +-
 hw/input/meson.build                              |   2 +-
 hw/misc/Kconfig                                   |   3 +
 hw/misc/meson.build                               |   3 +
 hw/misc/trace-events                              |  19 +
 hw/watchdog/trace-events                          |   6 +
 tests/qtest/meson.build                           |   2 +-
 tests/tcg/aarch64/Makefile.target                 |   6 +-
 56 files changed, 2302 insertions(+), 777 deletions(-)
 rename docs/specs/{edu.txt => edu.rst} (64%)
 rename docs/specs/{ivshmem-spec.txt => ivshmem-spec.rst} (88%)
 rename docs/specs/{pvpanic.txt => pvpanic.rst} (64%)
 create mode 100644 docs/specs/standard-vga.rst
 delete mode 100644 docs/specs/standard-vga.txt
 rename docs/specs/{virt-ctlr.txt => virt-ctlr.rst} (70%)
 create mode 100644 docs/specs/vmcoreinfo.rst
 delete mode 100644 docs/specs/vmcoreinfo.txt
 create mode 100644 docs/specs/vmgenid.rst
 delete mode 100644 docs/specs/vmgenid.txt
 create mode 100644 docs/specs/vmw_pvscsi-spec.rst
 delete mode 100644 docs/specs/vmw_pvscsi-spec.txt
 delete mode 100644 include/hw/input/gamepad.h
 create mode 100644 include/hw/input/stellaris_gamepad.h
 create mode 100644 include/hw/misc/xlnx-versal-trng.h
 create mode 100644 hw/input/stellaris_gamepad.c
 delete mode 100644 hw/input/stellaris_input.c
 create mode 100644 hw/misc/xlnx-versal-trng.c
 create mode 100644 tests/qtest/xlnx-versal-trng-test.c
 create mode 100644 tests/tcg/aarch64/sve-str.c

Re: [PULL 00/33] target-arm queue

[Stefan Hajnoczi]

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Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes.

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