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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2dc0f69sm51198615e9.13.2025.01.09.03.12.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Jan 2025 03:12:02 -0800 (PST) Message-ID: <03cf1b53-aa42-401e-af3b-e73890984be4@linaro.org> Date: Thu, 9 Jan 2025 12:12:01 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/5] semihosting: Reduce target specific code To: Richard Henderson , =?UTF-8?Q?Alex_Benn=C3=A9e?= Cc: qemu-devel@nongnu.org, Pierrick Bouvier , Alistair Francis , Kito Cheng , Keith Packard , Daniel Henrique Barboza , Thomas Huth , Paolo Bonzini , =?UTF-8?Q?Marc-Andr=C3=A9_Lureau?= References: <20250103171037.11265-1-philmd@linaro.org> <87h669ba39.fsf@draig.linaro.org> <14a2173f-e1b4-4290-99e5-c46b4153d800@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <14a2173f-e1b4-4290-99e5-c46b4153d800@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org +Paolo & Marc-André Lureau for chardev backend. On 8/1/25 23:53, Richard Henderson wrote: > On 1/8/25 07:26, Alex Bennée wrote: >> Philippe Mathieu-Daudé writes: >> >>> This series makes semihosting config.c and console.c >>> target agnostic, building them once, removing symbol >>> collision of the following functions in the single >>> binary: >> >> Queued to semihosting/next, thanks. >> >>>   - qemu_semihosting_chardev_init >>>   - qemu_semihosting_config_options >>>   - qemu_semihosting_config_opts >>>   - qemu_semihosting_enable >>>   - semihosting_arg_fallback >>>   - semihosting_enabled >>>   - semihosting_get_argc >>>   - semihosting_get_target >>> >>> This function is still problematic, being built for >>> each target: >>> >>>   - qemu_semihosting_guestfd_init >>> >>> Note, it depends on CONFIG_ARM_COMPATIBLE_SEMIHOSTING >>> which is target specific, so doesn't scale in a >>> heterogeneous setup like the ZynqMP machine, having >>> ARM cores with CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y and >>> MicroBlaze ones with CONFIG_ARM_COMPATIBLE_SEMIHOSTING=n. >> >> Does MicroBlaze even do semihosting? >> >>> I suppose the semihosting API needs rework to consider >>> the CPUClass? I'll let that investigation for the >>> maintainer ;) >> >> Hmm most of it is already handled as EXCP_SEMIHOST exceptions are dealt >> with withing the target specific exception handlers. >> do_common_semihosting could be renamed though - do_armc_semihosting() >> maybe? >> >> If we have the full list of CPUs at qemu_semihosting_chardev_init() time >> we could then selectively do the bits of qemu_semihosting_guestfd_init() >> depending on what combination we have. For normal open/read/write stuff >> I think they could co-exist. >> >> Two independent cores could still write to stdout (0) though. Fixing >> that would need a per-cpu semihosting config. What I'd expect here is one VC per semihosting context stdout. If we want to mux, we use the chardev mux. Anyhow this in particular is not a blocker, it was just an opened question. > None of the semihosting stuff is smp safe. > > The assumption in the homogeneous cpu case is that the guest uses it's > own mutexes to protect the semihosting calls.  This is obviously more > complicated in the heterogeneous case, but it *still* should not be > qemu's problem. FYI the use case requested is $n Hexagon cores writing to $n semihosting file descriptors, and a user-mode process on an ARM core able to read each of these FDs. Regards, Phil.