Re: [PATCH-for-9.1 v2 2/2] hw/pci-host/gt64120: Set PCI base address register write mask

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

On 1/8/24 17:02, Michael S. Tsirkin wrote:
> On Thu, Aug 01, 2024 at 04:56:30PM +0200, Philippe Mathieu-Daudé wrote:
>> When booting Linux we see:
>>
>>    PCI host bridge to bus 0000:00
>>    pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff]
>>    pci_bus 0000:00: root bus resource [io  0x1000-0x1fffff]
>>    pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
>>    pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000
>>    pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size)
>>    pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size)
>>    pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size)
>>    pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size)
>>    pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size)
>>
>> This is due to missing base address register write mask.
>> Add it to get:
>>
>>    PCI host bridge to bus 0000:00
>>    pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff]
>>    pci_bus 0000:00: root bus resource [io  0x1000-0x1fffff]
>>    pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
>>    pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000
>>    pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref]
>>    pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref]
>>    pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff]
>>    pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff]
>>    pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff]
>>    pci 0000:00:00.0: reg 0x24: [io  0x14000000-0x14000007]
>>
>> Mention the datasheet referenced. Remove the "Malta assumptions ahead"
>> comment since the reset values from the datasheet are used.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   hw/pci-host/gt64120.c | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c
>> index b68d647753..344baf55db 100644
>> --- a/hw/pci-host/gt64120.c
>> +++ b/hw/pci-host/gt64120.c
>> @@ -1224,6 +1224,13 @@ static void gt64120_pci_reset_hold(Object *obj, ResetType type)
>>                    PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
>>       pci_config_set_prog_interface(d->config, 0);
>>   
>> +    pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff009);
>> +    pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff009);
>> +    pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff009);
>> +    pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff009);
>> +    pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff009);
>> +    pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001);
>> +
>>       pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
>>       pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
>>       pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
> 
> 
> if you are tweaking wmask, I think migration will fail.
> So you have to make this depend on machine property, and
> put in compat machinery.

Fortunately we don't need because this device is only meant to
be used by MIPS machines which aren't versioned.

I'll mention that in the description.