* [PATCH-for-9.1 v2 0/2] hw/pci-host/gt64120: Set PCI base address register write mask @ 2024-08-01 14:56 Philippe Mathieu-Daudé 2024-08-01 14:56 ` [PATCH-for-9.1 v2 1/2] hw/pci-host/gt64120: Reset config registers during RESET phase Philippe Mathieu-Daudé 2024-08-01 14:56 ` [PATCH-for-9.1 v2 2/2] hw/pci-host/gt64120: Set PCI base address register write mask Philippe Mathieu-Daudé 0 siblings, 2 replies; 8+ messages in thread From: Philippe Mathieu-Daudé @ 2024-08-01 14:56 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, Aurelien Jarno, Michael S . Tsirkin v2: Move reset values from Realize to ResetHold (mst) Philippe Mathieu-Daudé (2): hw/pci-host/gt64120: Reset config registers during RESET phase hw/pci-host/gt64120: Set PCI base address register write mask hw/pci-host/gt64120.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) -- 2.45.2 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH-for-9.1 v2 1/2] hw/pci-host/gt64120: Reset config registers during RESET phase 2024-08-01 14:56 [PATCH-for-9.1 v2 0/2] hw/pci-host/gt64120: Set PCI base address register write mask Philippe Mathieu-Daudé @ 2024-08-01 14:56 ` Philippe Mathieu-Daudé 2024-08-01 14:56 ` [PATCH-for-9.1 v2 2/2] hw/pci-host/gt64120: Set PCI base address register write mask Philippe Mathieu-Daudé 1 sibling, 0 replies; 8+ messages in thread From: Philippe Mathieu-Daudé @ 2024-08-01 14:56 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, Aurelien Jarno, Michael S . Tsirkin Reset config values in the device RESET phase, not only once when the device is realized, because otherwise the device can use unknown values at reset. Reported-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- hw/pci-host/gt64120.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index e02efc9e2e..b68d647753 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -1,6 +1,8 @@ /* * QEMU GT64120 PCI host * + * (Datasheet GT-64120 Rev 1.4 from Sep 14, 1999) + * * Copyright (c) 2006,2007 Aurelien Jarno * * Permission is hereby granted, free of charge, to any person obtaining a copy @@ -1211,19 +1213,24 @@ static void gt64120_realize(DeviceState *dev, Error **errp) empty_slot_init("GT64120", 0, 0x20000000); } -static void gt64120_pci_realize(PCIDevice *d, Error **errp) +static void gt64120_pci_reset_hold(Object *obj, ResetType type) { - /* FIXME: Malta specific hw assumptions ahead */ + PCIDevice *d = PCI_DEVICE(obj); + + /* Values from chapter 17.16 "PCI Configuration" */ + pci_set_word(d->config + PCI_COMMAND, 0); pci_set_word(d->config + PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); pci_config_set_prog_interface(d->config, 0); + pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000); pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000); pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001); + pci_set_byte(d->config + 0x3d, 0x01); } @@ -1231,8 +1238,9 @@ static void gt64120_pci_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); - k->realize = gt64120_pci_realize; + rc->phases.hold = gt64120_pci_reset_hold; k->vendor_id = PCI_VENDOR_ID_MARVELL; k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X; k->revision = 0x10; -- 2.45.2 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH-for-9.1 v2 2/2] hw/pci-host/gt64120: Set PCI base address register write mask 2024-08-01 14:56 [PATCH-for-9.1 v2 0/2] hw/pci-host/gt64120: Set PCI base address register write mask Philippe Mathieu-Daudé 2024-08-01 14:56 ` [PATCH-for-9.1 v2 1/2] hw/pci-host/gt64120: Reset config registers during RESET phase Philippe Mathieu-Daudé @ 2024-08-01 14:56 ` Philippe Mathieu-Daudé 2024-08-01 14:59 ` Philippe Mathieu-Daudé ` (2 more replies) 1 sibling, 3 replies; 8+ messages in thread From: Philippe Mathieu-Daudé @ 2024-08-01 14:56 UTC (permalink / raw) To: qemu-devel Cc: Philippe Mathieu-Daudé, Aurelien Jarno, Michael S . Tsirkin When booting Linux we see: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size) This is due to missing base address register write mask. Add it to get: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref] pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref] pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff] pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff] pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff] pci 0000:00:00.0: reg 0x24: [io 0x14000000-0x14000007] Mention the datasheet referenced. Remove the "Malta assumptions ahead" comment since the reset values from the datasheet are used. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- hw/pci-host/gt64120.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index b68d647753..344baf55db 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -1224,6 +1224,13 @@ static void gt64120_pci_reset_hold(Object *obj, ResetType type) PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); pci_config_set_prog_interface(d->config, 0); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); + pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); -- 2.45.2 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH-for-9.1 v2 2/2] hw/pci-host/gt64120: Set PCI base address register write mask 2024-08-01 14:56 ` [PATCH-for-9.1 v2 2/2] hw/pci-host/gt64120: Set PCI base address register write mask Philippe Mathieu-Daudé @ 2024-08-01 14:59 ` Philippe Mathieu-Daudé 2024-08-01 15:02 ` Michael S. Tsirkin 2024-08-01 15:03 ` Michael S. Tsirkin 2 siblings, 0 replies; 8+ messages in thread From: Philippe Mathieu-Daudé @ 2024-08-01 14:59 UTC (permalink / raw) To: qemu-devel; +Cc: Aurelien Jarno, Michael S . Tsirkin On 1/8/24 16:56, Philippe Mathieu-Daudé wrote: > When booting Linux we see: > > PCI host bridge to bus 0000:00 > pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] > pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] > pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] > pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 > pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size) > > This is due to missing base address register write mask. > Add it to get: > > PCI host bridge to bus 0000:00 > pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] > pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] > pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] > pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 > pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref] > pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref] > pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff] > pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff] > pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff] > pci 0000:00:00.0: reg 0x24: [io 0x14000000-0x14000007] > > Mention the datasheet referenced. Remove the "Malta assumptions ahead" > comment since the reset values from the datasheet are used. Argh this comment belongs to the previous patch :/ > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > hw/pci-host/gt64120.c | 7 +++++++ > 1 file changed, 7 insertions(+) ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH-for-9.1 v2 2/2] hw/pci-host/gt64120: Set PCI base address register write mask 2024-08-01 14:56 ` [PATCH-for-9.1 v2 2/2] hw/pci-host/gt64120: Set PCI base address register write mask Philippe Mathieu-Daudé 2024-08-01 14:59 ` Philippe Mathieu-Daudé @ 2024-08-01 15:02 ` Michael S. Tsirkin 2024-08-01 16:51 ` Philippe Mathieu-Daudé 2024-08-01 16:51 ` Philippe Mathieu-Daudé 2024-08-01 15:03 ` Michael S. Tsirkin 2 siblings, 2 replies; 8+ messages in thread From: Michael S. Tsirkin @ 2024-08-01 15:02 UTC (permalink / raw) To: Philippe Mathieu-Daudé; +Cc: qemu-devel, Aurelien Jarno On Thu, Aug 01, 2024 at 04:56:30PM +0200, Philippe Mathieu-Daudé wrote: > When booting Linux we see: > > PCI host bridge to bus 0000:00 > pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] > pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] > pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] > pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 > pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size) > > This is due to missing base address register write mask. > Add it to get: > > PCI host bridge to bus 0000:00 > pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] > pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] > pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] > pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 > pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref] > pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref] > pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff] > pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff] > pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff] > pci 0000:00:00.0: reg 0x24: [io 0x14000000-0x14000007] > > Mention the datasheet referenced. Remove the "Malta assumptions ahead" > comment since the reset values from the datasheet are used. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > hw/pci-host/gt64120.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c > index b68d647753..344baf55db 100644 > --- a/hw/pci-host/gt64120.c > +++ b/hw/pci-host/gt64120.c > @@ -1224,6 +1224,13 @@ static void gt64120_pci_reset_hold(Object *obj, ResetType type) > PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); > pci_config_set_prog_interface(d->config, 0); > > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); > + > pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); > pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); > pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); if you are tweaking wmask, I think migration will fail. So you have to make this depend on machine property, and put in compat machinery. > -- > 2.45.2 ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH-for-9.1 v2 2/2] hw/pci-host/gt64120: Set PCI base address register write mask 2024-08-01 15:02 ` Michael S. Tsirkin @ 2024-08-01 16:51 ` Philippe Mathieu-Daudé 2024-08-01 16:51 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 8+ messages in thread From: Philippe Mathieu-Daudé @ 2024-08-01 16:51 UTC (permalink / raw) To: Michael S. Tsirkin; +Cc: qemu-devel, Aurelien Jarno On 1/8/24 17:02, Michael S. Tsirkin wrote: > On Thu, Aug 01, 2024 at 04:56:30PM +0200, Philippe Mathieu-Daudé wrote: >> When booting Linux we see: >> >> PCI host bridge to bus 0000:00 >> pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] >> pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] >> pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] >> pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 >> pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) >> pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) >> pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size) >> pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size) >> pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size) >> >> This is due to missing base address register write mask. >> Add it to get: >> >> PCI host bridge to bus 0000:00 >> pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] >> pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] >> pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] >> pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 >> pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref] >> pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref] >> pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff] >> pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff] >> pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff] >> pci 0000:00:00.0: reg 0x24: [io 0x14000000-0x14000007] >> >> Mention the datasheet referenced. Remove the "Malta assumptions ahead" >> comment since the reset values from the datasheet are used. >> >> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >> --- >> hw/pci-host/gt64120.c | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c >> index b68d647753..344baf55db 100644 >> --- a/hw/pci-host/gt64120.c >> +++ b/hw/pci-host/gt64120.c >> @@ -1224,6 +1224,13 @@ static void gt64120_pci_reset_hold(Object *obj, ResetType type) >> PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); >> pci_config_set_prog_interface(d->config, 0); >> >> + pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff009); >> + pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff009); >> + pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff009); >> + pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff009); >> + pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff009); >> + pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); >> + >> pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); >> pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); >> pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); > > > if you are tweaking wmask, I think migration will fail. > So you have to make this depend on machine property, and > put in compat machinery. Fortunately we don't need because this device is only meant to be used by MIPS machines which aren't versioned. ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH-for-9.1 v2 2/2] hw/pci-host/gt64120: Set PCI base address register write mask 2024-08-01 15:02 ` Michael S. Tsirkin 2024-08-01 16:51 ` Philippe Mathieu-Daudé @ 2024-08-01 16:51 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 8+ messages in thread From: Philippe Mathieu-Daudé @ 2024-08-01 16:51 UTC (permalink / raw) To: Michael S. Tsirkin; +Cc: qemu-devel, Aurelien Jarno On 1/8/24 17:02, Michael S. Tsirkin wrote: > On Thu, Aug 01, 2024 at 04:56:30PM +0200, Philippe Mathieu-Daudé wrote: >> When booting Linux we see: >> >> PCI host bridge to bus 0000:00 >> pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] >> pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] >> pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] >> pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 >> pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) >> pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) >> pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size) >> pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size) >> pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size) >> >> This is due to missing base address register write mask. >> Add it to get: >> >> PCI host bridge to bus 0000:00 >> pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] >> pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] >> pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] >> pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 >> pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref] >> pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref] >> pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff] >> pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff] >> pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff] >> pci 0000:00:00.0: reg 0x24: [io 0x14000000-0x14000007] >> >> Mention the datasheet referenced. Remove the "Malta assumptions ahead" >> comment since the reset values from the datasheet are used. >> >> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >> --- >> hw/pci-host/gt64120.c | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c >> index b68d647753..344baf55db 100644 >> --- a/hw/pci-host/gt64120.c >> +++ b/hw/pci-host/gt64120.c >> @@ -1224,6 +1224,13 @@ static void gt64120_pci_reset_hold(Object *obj, ResetType type) >> PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); >> pci_config_set_prog_interface(d->config, 0); >> >> + pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff009); >> + pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff009); >> + pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff009); >> + pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff009); >> + pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff009); >> + pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); >> + >> pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); >> pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); >> pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); > > > if you are tweaking wmask, I think migration will fail. > So you have to make this depend on machine property, and > put in compat machinery. Fortunately we don't need because this device is only meant to be used by MIPS machines which aren't versioned. I'll mention that in the description. ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH-for-9.1 v2 2/2] hw/pci-host/gt64120: Set PCI base address register write mask 2024-08-01 14:56 ` [PATCH-for-9.1 v2 2/2] hw/pci-host/gt64120: Set PCI base address register write mask Philippe Mathieu-Daudé 2024-08-01 14:59 ` Philippe Mathieu-Daudé 2024-08-01 15:02 ` Michael S. Tsirkin @ 2024-08-01 15:03 ` Michael S. Tsirkin 2 siblings, 0 replies; 8+ messages in thread From: Michael S. Tsirkin @ 2024-08-01 15:03 UTC (permalink / raw) To: Philippe Mathieu-Daudé; +Cc: qemu-devel, Aurelien Jarno On Thu, Aug 01, 2024 at 04:56:30PM +0200, Philippe Mathieu-Daudé wrote: > When booting Linux we see: > > PCI host bridge to bus 0000:00 > pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] > pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] > pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] > pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 > pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size) > pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size) > > This is due to missing base address register write mask. > Add it to get: > > PCI host bridge to bus 0000:00 > pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] > pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] > pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] > pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 > pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref] > pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref] > pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff] > pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff] > pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff] > pci 0000:00:00.0: reg 0x24: [io 0x14000000-0x14000007] > > Mention the datasheet referenced. Remove the "Malta assumptions ahead" > comment since the reset values from the datasheet are used. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > hw/pci-host/gt64120.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c > index b68d647753..344baf55db 100644 > --- a/hw/pci-host/gt64120.c > +++ b/hw/pci-host/gt64120.c > @@ -1224,6 +1224,13 @@ static void gt64120_pci_reset_hold(Object *obj, ResetType type) > PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); > pci_config_set_prog_interface(d->config, 0); > > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff009); > + pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); > + weird to change wmask on reset. > pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); > pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); > pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); > -- > 2.45.2 ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-08-01 16:52 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-08-01 14:56 [PATCH-for-9.1 v2 0/2] hw/pci-host/gt64120: Set PCI base address register write mask Philippe Mathieu-Daudé 2024-08-01 14:56 ` [PATCH-for-9.1 v2 1/2] hw/pci-host/gt64120: Reset config registers during RESET phase Philippe Mathieu-Daudé 2024-08-01 14:56 ` [PATCH-for-9.1 v2 2/2] hw/pci-host/gt64120: Set PCI base address register write mask Philippe Mathieu-Daudé 2024-08-01 14:59 ` Philippe Mathieu-Daudé 2024-08-01 15:02 ` Michael S. Tsirkin 2024-08-01 16:51 ` Philippe Mathieu-Daudé 2024-08-01 16:51 ` Philippe Mathieu-Daudé 2024-08-01 15:03 ` Michael S. Tsirkin
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